diff --git a/src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-3secs-of-booting-time.patch b/src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch similarity index 83% rename from src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-3secs-of-booting-time.patch rename to src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch index 2ede8e39..cf1c707c 100644 --- a/src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-3secs-of-booting-time.patch +++ b/src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch @@ -1,9 +1,9 @@ From 6061bcfb8f1dfc47714beae179be4bc4e4223062 Mon Sep 17 00:00:00 2001 From: Rockefeller Lin Date: Fri, 7 Apr 2023 03:29:44 +0000 -Subject: [PATCH] Set bootdelay to 0 to save ~3secs of booting time +Subject: [PATCH] Set bootdelay to 0 to save ~2secs of booting time -Set bootdelay to 0 to save ~3secs of booting time +Set bootdelay to 0 to save ~2secs of booting time --- configs/mt8365_sb35_defconfig | 1 + 1 files changed, 1 insertions(+) diff --git a/src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb b/src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb index 0ff3cbde..b9e3fb46 100644 --- a/src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb +++ b/src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb @@ -6,5 +6,5 @@ SRC_URI += " \ file://fw_env.config \ file://0001-Add-dedicated-sb35-defconfig-and-dts-files.patch \ file://0002-Remove-DPI-and-it66121-from-sb35-dts.patch \ - file://0001-Set-bootdelay-to-0-to-save-3secs-of-booting-time.patch \ + file://0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch \ " diff --git a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-lt9611-porting.patch b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-lt9611-porting.patch index f742144f..3f8cb2ad 100644 --- a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-lt9611-porting.patch +++ b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-lt9611-porting.patch @@ -1,18 +1,27 @@ -From 94daedcf534be4762f11c8ab921263540884c5f2 Mon Sep 17 00:00:00 2001 +From 2bbf0418c583d931056a70d05658e7140cf78f32 Mon Sep 17 00:00:00 2001 From: Rockefeller Lin Date: Wed, 17 May 2023 11:35:51 +0800 -Subject: [PATCH 1/1] lt9611 porting +Subject: [PATCH] lt9611 porting --- - arch/arm64/boot/dts/mediatek/mt8365-sb35.dts | 28 +++++++++++++++++++- - drivers/gpu/drm/bridge/lontium-lt9611.c | 19 +++++++++++++ - 2 files changed, 46 insertions(+), 1 deletion(-) + arch/arm64/boot/dts/mediatek/mt8365-sb35.dts | 36 ++++++++++++++++++-- + 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts -index f226ec49bc2f..e8260faaab55 100644 +index f226ec49bc2f..4ba2e16e18f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts -@@ -321,7 +321,7 @@ hdmi-bridge@3b { +@@ -171,6 +171,9 @@ hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c2>; ++ pinctrl-0 = <&hdmi_ddc_pins>; ++ pinctrl-names = "default"; ++ ddc-en-gpios = <&pio 4 GPIO_ACTIVE_HIGH>; + + port { + hdmi_con: endpoint { +@@ -321,7 +324,7 @@ hdmi-bridge@3b { compatible = "lontium,lt9611"; reg = <0x3b>; pinctrl-0 = <&hdmi_pins>; @@ -21,11 +30,20 @@ index f226ec49bc2f..e8260faaab55 100644 reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; interrupts-extended = <&pio 125 IRQ_TYPE_EDGE_FALLING>; -@@ -657,6 +657,32 @@ pin_pwr_en { +@@ -652,13 +655,42 @@ pin_ethernet_reset { + }; + }; + +- hdmi_pins: hdmi-pins { ++ hdmi_ddc_pins: hdmi-ddc-pins { + pin_pwr_en { pinmux = ; output-high; }; + }; + + ++ hdmi_pins: hdmi-pins { + pin_lt9611_1v8_en { + pinmux = ; + output-low; @@ -51,39 +69,11 @@ index f226ec49bc2f..e8260faaab55 100644 + pinmux = ; + output-low; + }; - }; - - keypad_pins: keypad-pins { -diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c -index 45acff6014e1..7442e14f564f 100644 ---- a/drivers/gpu/drm/bridge/lontium-lt9611.c -+++ b/drivers/gpu/drm/bridge/lontium-lt9611.c -@@ -882,6 +882,25 @@ static struct edid *lt9611_bridge_get_edid(struct drm_bridge *bridge, - { - struct lt9611 *lt9611 = bridge_to_lt9611(bridge); - -+ if (of_device_is_compatible(lt9611->next_bridge->of_node, "hdmi-connector")) { -+ struct i2c_adapter *ddc; -+ struct device_node *ddc_node; ++ }; + -+ ddc_node = of_parse_phandle(lt9611->next_bridge->of_node, "ddc-i2c-bus", 0); -+ if (ddc_node) { -+ ddc = of_find_i2c_adapter_by_node(ddc_node); -+ of_node_put(ddc_node); -+ -+ if (ddc) -+ return drm_get_edid(connector, ddc); -+ else -+ dev_err(lt9611->dev, "The ddc i2c adapter found by node is not ready yet!\n"); -+ } else { -+ dev_err(lt9611->dev, "Failed to find ddc-i2c-bus node in %pOF\n", -+ lt9611->next_bridge->of_node); -+ } -+ } -+ - lt9611_power_on(lt9611); - return drm_do_get_edid(connector, lt9611_get_edid_block, lt9611); - } + keypad_pins: keypad-pins { + pins_cols { + pinmux = , -- 2.25.1 diff --git a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-UART_EFR-register-address.patch b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-UART_EFR-register-address.patch new file mode 100644 index 00000000..4bb120a5 --- /dev/null +++ b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-UART_EFR-register-address.patch @@ -0,0 +1,95 @@ +From d01eb92f8b42acfa775aaf738dd99e6bf7d4c812 Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 27 Apr 2022 15:23:26 +0200 +Subject: [PATCH 1/1] serial: 8250_mtk: Fix UART_EFR register address + +commit bb0b197aadd928f52ce6f01f0ee977f0a08cf1be upstream. + +On MediaTek SoCs, the UART IP is 16550A compatible, but there are some +specific quirks: we are declaring a register shift of 2, but this is +only valid for the majority of the registers, as there are some that +are out of the standard layout. + +Specifically, this driver is using definitions from serial_reg.h, where +we have a UART_EFR register defined as 2: this results in a 0x8 offset, +but there we have the FCR register instead. + +The right offset for the EFR register on MediaTek UART is at 0x98, +so, following the decimal definition convention in serial_reg.h and +accounting for the register left shift of two, add and use the correct +register address for this IP, defined as decimal 38, so that the final +calculation results in (0x26 << 2) = 0x98. + +Fixes: bdbd0a7f8f03 ("serial: 8250-mtk: modify baudrate setting") +Signed-off-by: AngeloGioacchino Del Regno +Cc: stable +Link: https://lore.kernel.org/r/20220427132328.228297-2-angelogioacchino.delregno@collabora.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/8250/8250_mtk.c | 15 ++++++++------- + 1 file changed, 8 insertions(+), 7 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c +index fb65dc601b23..a561aceb73ed 100644 +--- a/drivers/tty/serial/8250/8250_mtk.c ++++ b/drivers/tty/serial/8250/8250_mtk.c +@@ -37,6 +37,7 @@ + #define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */ + #define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */ + ++#define MTK_UART_EFR 38 /* I/O: Extended Features Register */ + #define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */ + #define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */ + #define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */ +@@ -169,7 +170,7 @@ static void mtk8250_dma_enable(struct uart_8250_port *up) + MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX); + + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); +- serial_out(up, UART_EFR, UART_EFR_ECB); ++ serial_out(up, MTK_UART_EFR, UART_EFR_ECB); + serial_out(up, UART_LCR, lcr); + + if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0) +@@ -232,7 +233,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) + int lcr = serial_in(up, UART_LCR); + + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); +- serial_out(up, UART_EFR, UART_EFR_ECB); ++ serial_out(up, MTK_UART_EFR, UART_EFR_ECB); + serial_out(up, UART_LCR, lcr); + lcr = serial_in(up, UART_LCR); + +@@ -241,7 +242,7 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) + serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); + serial_out(up, MTK_UART_ESCAPE_EN, 0x00); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); +- serial_out(up, UART_EFR, serial_in(up, UART_EFR) & ++ serial_out(up, MTK_UART_EFR, serial_in(up, MTK_UART_EFR) & + (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))); + serial_out(up, UART_LCR, lcr); + mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI | +@@ -255,8 +256,8 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + + /*enable hw flow control*/ +- serial_out(up, UART_EFR, MTK_UART_EFR_HW_FC | +- (serial_in(up, UART_EFR) & ++ serial_out(up, MTK_UART_EFR, MTK_UART_EFR_HW_FC | ++ (serial_in(up, MTK_UART_EFR) & + (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); + + serial_out(up, UART_LCR, lcr); +@@ -270,8 +271,8 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); + + /*enable sw flow control */ +- serial_out(up, UART_EFR, MTK_UART_EFR_XON1_XOFF1 | +- (serial_in(up, UART_EFR) & ++ serial_out(up, MTK_UART_EFR, MTK_UART_EFR_XON1_XOFF1 | ++ (serial_in(up, MTK_UART_EFR) & + (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); + + serial_out(up, UART_XON1, START_CHAR(port->state->port.tty)); +-- +2.25.1 + diff --git a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-register-address-for-XON-XOFF-ch.patch b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-register-address-for-XON-XOFF-ch.patch new file mode 100644 index 00000000..96434286 --- /dev/null +++ b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0001-serial-8250_mtk-Fix-register-address-for-XON-XOFF-ch.patch @@ -0,0 +1,48 @@ +From 73e12d4d33bcf04fc076382492d1cc56b77cd6af Mon Sep 17 00:00:00 2001 +From: AngeloGioacchino Del Regno +Date: Wed, 27 Apr 2022 15:23:28 +0200 +Subject: [PATCH 1/1] serial: 8250_mtk: Fix register address for XON/XOFF + character + +commit e1bfdbc7daca171c74a577b3dd0b36d76bb0ffcc upstream. + +The XON1/XOFF1 character registers are at offset 0xa0 and 0xa8 +respectively, so we cannot use the definition in serial_port.h. + +Fixes: bdbd0a7f8f03 ("serial: 8250-mtk: modify baudrate setting") +Signed-off-by: AngeloGioacchino Del Regno +Cc: stable +Link: https://lore.kernel.org/r/20220427132328.228297-4-angelogioacchino.delregno@collabora.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/8250/8250_mtk.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/tty/serial/8250/8250_mtk.c b/drivers/tty/serial/8250/8250_mtk.c +index a561aceb73ed..de48a58460f4 100644 +--- a/drivers/tty/serial/8250/8250_mtk.c ++++ b/drivers/tty/serial/8250/8250_mtk.c +@@ -54,6 +54,9 @@ + #define MTK_UART_TX_TRIGGER 1 + #define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE + ++#define MTK_UART_XON1 40 /* I/O: Xon character 1 */ ++#define MTK_UART_XOFF1 42 /* I/O: Xoff character 1 */ ++ + #ifdef CONFIG_SERIAL_8250_DMA + enum dma_rx_status { + DMA_RX_START = 0, +@@ -275,8 +278,8 @@ static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) + (serial_in(up, MTK_UART_EFR) & + (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); + +- serial_out(up, UART_XON1, START_CHAR(port->state->port.tty)); +- serial_out(up, UART_XOFF1, STOP_CHAR(port->state->port.tty)); ++ serial_out(up, MTK_UART_XON1, START_CHAR(port->state->port.tty)); ++ serial_out(up, MTK_UART_XOFF1, STOP_CHAR(port->state->port.tty)); + serial_out(up, UART_LCR, lcr); + mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI); + mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI); +-- +2.25.1 + diff --git a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0002-lt9611-porting-revise-delay.patch b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0002-lt9611-porting-revise-delay.patch new file mode 100644 index 00000000..6353aa2d --- /dev/null +++ b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0002-lt9611-porting-revise-delay.patch @@ -0,0 +1,35 @@ +From 9b14196f2c3956bf976d3b767789580c4b5439f1 Mon Sep 17 00:00:00 2001 +From: Rockefeller Lin +Date: Tue, 6 Jun 2023 09:12:00 +0800 +Subject: [PATCH] lt9611 porting:revise delay + +Shorten/remove some delays to save boot time. +--- + drivers/gpu/drm/bridge/lontium-lt9611.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c +index 7442e14f564f..0c814d06cbd0 100644 +--- a/drivers/gpu/drm/bridge/lontium-lt9611.c ++++ b/drivers/gpu/drm/bridge/lontium-lt9611.c +@@ -536,7 +536,7 @@ static void lt9611_reset(struct lt9611 *lt9611) + msleep(20); + + gpiod_set_value_cansleep(lt9611->reset_gpio, 1); +- msleep(100); ++ msleep(20); + } + + static void lt9611_assert_5v(struct lt9611 *lt9611) +@@ -719,7 +719,7 @@ lt9611_bridge_atomic_enable(struct drm_bridge *bridge, + lt9611_hdmi_tx_digital(lt9611); + lt9611_hdmi_tx_phy(lt9611); + +- msleep(500); ++ //msleep(500); + + lt9611_video_check(lt9611); + +-- +2.25.1 + diff --git a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk_5.15.bb b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk_5.15.bb index f0d5c0a2..290849d8 100644 --- a/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk_5.15.bb +++ b/src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk_5.15.bb @@ -32,6 +32,9 @@ SRC_URI += " \ file://0008-drm-bridge-lt9611-rework-infoframes-handling.patch \ file://0009-drm-bridge-lt9611-stop-filtering-modes-via-the-table.patch \ file://0001-lt9611-porting.patch \ + file://0002-lt9611-porting-revise-delay.patch \ file://0001-Audio-RT5509-driver-porting.patch \ file://0001-Add-stereo-mode-support.patch \ + file://0001-serial-8250_mtk-Fix-UART_EFR-register-address.patch \ + file://0001-serial-8250_mtk-Fix-register-address-for-XON-XOFF-ch.patch \ "