Bug #145 » inno_for_sb35_rity-kirkstone-v23.2-v001_0509.patch
| src/meta-mediatek-bsp/classes/image_type_aiotflash.bbclass 2024-05-07 15:25:40.802613474 +0800 → src/meta-mediatek-bsp/classes/image_type_aiotflash.bbclass 2024-05-07 14:53:42.755175200 +0800 | ||
|---|---|---|
| 44 | 44 |
cp -a ${DEPLOY_DIR_IMAGE}/rity.json ${tmp_pack_dir}
|
| 45 | 45 |
cp -a ${DEPLOY_DIR_IMAGE}/partitions.json ${tmp_pack_dir}
|
| 46 | 46 |
cp -a ${DEPLOY_DIR_IMAGE}/lk.bin ${tmp_pack_dir}
|
| 47 |
cp -a ${DEPLOY_DIR_IMAGE}/devicetree ${tmp_pack_dir}
|
|
| 47 | 48 | |
| 48 | 49 |
if [ "${@oe.utils.conditional('BL2_SIGN_ENABLE', '1', '1', '', d)}" = "1" ]; then
|
| 49 | 50 |
cp -a ${DEPLOY_DIR_IMAGE}/efuse.cfg ${tmp_pack_dir}
|
| src/meta-mediatek-bsp/conf/machine/mt8365-sb35.conf 2024-05-07 15:25:40.806613536 +0800 → src/meta-mediatek-bsp/conf/machine/mt8365-sb35.conf 2024-05-07 14:54:19.963681600 +0800 | ||
|---|---|---|
| 5 | 5 |
KERNEL_DEVICETREE = "mediatek/mt8365-sb35.dtb" |
| 6 | 6 | |
| 7 | 7 |
# U-Boot |
| 8 |
UBOOT_MACHINE = "mt8365_pumpkin_defconfig"
|
|
| 8 |
UBOOT_MACHINE = "mt8365_sb35_defconfig"
|
|
| 9 | 9 | |
| 10 | 10 |
# libdram |
| 11 | 11 |
LIBDRAM_BOARD_NAME = "mt8365-sb35" |
| ... | ... | |
| 13 | 13 |
# LK |
| 14 | 14 |
LK_BOARD_NAME = "${LIBDRAM_BOARD_NAME}"
|
| 15 | 15 | |
| 16 |
MACHINE_FEATURES:append = " alsa usbgadget usbhost wifi" |
|
| 16 |
MACHINE_FEATURES:append = " alsa usbgadget usbhost wifi screen"
|
|
| 17 | 17 | |
| 18 | 18 |
MACHINEOVERRIDES =. "mt8365-sb35:i350-sb35:genio-350-sb35:" |
| src/meta-mediatek-bsp/recipes-bsp/alsa-state/mt8365-sb35/asound.conf 2024-05-07 15:25:40.810613597 +0800 → src/meta-mediatek-bsp/recipes-bsp/alsa-state/mt8365-sb35/asound.conf 2024-05-07 14:55:18.148731800 +0800 | ||
|---|---|---|
| 22 | 22 |
} |
| 23 | 23 |
} |
| 24 | 24 | |
| 25 |
pcm.speaker {
|
|
| 26 |
type plug |
|
| 27 |
slave {
|
|
| 28 |
pcm "hw:mtsndcard,1,0" |
|
| 29 |
channels 2 |
|
| 30 |
} |
|
| 31 |
} |
|
| 32 | ||
| 25 | 33 |
pcm.line {
|
| 26 | 34 |
type asym |
| 27 | 35 |
playback.pcm "jack_speaker" |
| src/meta-mediatek-bsp/recipes-bsp/alsa-state/mt8365-sb35/asound.state 2024-05-07 15:25:40.810613597 +0800 → src/meta-mediatek-bsp/recipes-bsp/alsa-state/mt8365-sb35/asound.state 2024-05-07 14:55:39.326596000 +0800 | ||
|---|---|---|
| 12 | 12 |
control.2 {
|
| 13 | 13 |
iface MIXER |
| 14 | 14 |
name 'O00 I07 Switch' |
| 15 |
value false
|
|
| 15 |
value true
|
|
| 16 | 16 |
comment {
|
| 17 | 17 |
access 'read write' |
| 18 | 18 |
type BOOLEAN |
| ... | ... | |
| 32 | 32 |
control.4 {
|
| 33 | 33 |
iface MIXER |
| 34 | 34 |
name 'O01 I08 Switch' |
| 35 |
value false
|
|
| 35 |
value true
|
|
| 36 | 36 |
comment {
|
| 37 | 37 |
access 'read write' |
| 38 | 38 |
type BOOLEAN |
| src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Add-dedicated-sb35-defconfig-and-dts-files.patch 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Add-dedicated-sb35-defconfig-and-dts-files.patch 2024-05-07 15:04:48.402525900 +0800 | ||
|---|---|---|
| 1 |
From 05bb8f47e4d376d05f30ef95b170ac51aaac6478 Mon Sep 17 00:00:00 2001 |
|
| 2 |
From: Rockefeller Lin <rockefeller.lin@innocomm.com> |
|
| 3 |
Date: Wed, 24 May 2023 12:18:47 +0800 |
|
| 4 |
Subject: [PATCH 1/1] Add dedicated sb35 defconfig and dts files |
|
| 5 | ||
| 6 |
The defconfig and dts files are copied from mt8365-pumpkin. |
|
| 7 |
--- |
|
| 8 |
arch/arm/dts/Makefile | 1 + |
|
| 9 |
arch/arm/dts/mt8365-sb35.dts | 164 ++++++++++++++++++++++++++++++++++ |
|
| 10 |
configs/mt8365_sb35_defconfig | 97 ++++++++++++++++++++ |
|
| 11 |
3 files changed, 262 insertions(+) |
|
| 12 |
create mode 100644 arch/arm/dts/mt8365-sb35.dts |
|
| 13 |
create mode 100644 configs/mt8365_sb35_defconfig |
|
| 14 | ||
| 15 |
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile |
|
| 16 |
index 7b216bf62a..ac852fab60 100644 |
|
| 17 |
--- a/arch/arm/dts/Makefile |
|
| 18 |
+++ b/arch/arm/dts/Makefile |
|
| 19 |
@@ -1237,6 +1237,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ |
|
| 20 |
mt8195-demo.dtb \ |
|
| 21 |
mt8195-evb-ufs.dtb \ |
|
| 22 |
mt8365-pumpkin.dtb \ |
|
| 23 |
+ mt8365-sb35.dtb \ |
|
| 24 |
mt8512-bm1-emmc.dtb \ |
|
| 25 |
mt8516-pumpkin.dtb \ |
|
| 26 |
mt8518-ap1-emmc.dtb \ |
|
| 27 |
diff --git a/arch/arm/dts/mt8365-sb35.dts b/arch/arm/dts/mt8365-sb35.dts |
|
| 28 |
new file mode 100644 |
|
| 29 |
index 0000000000..5f57657026 |
|
| 30 |
--- /dev/null |
|
| 31 |
+++ b/arch/arm/dts/mt8365-sb35.dts |
|
| 32 |
@@ -0,0 +1,164 @@ |
|
| 33 |
+// SPDX-License-Identifier: GPL-2.0 OR MIT |
|
| 34 |
+/* |
|
| 35 |
+ * Copyright (C) 2021 BayLibre SAS. |
|
| 36 |
+ * Author: Fabien Parent <fparent@baylibre.com> |
|
| 37 |
+ */ |
|
| 38 |
+ |
|
| 39 |
+/dts-v1/; |
|
| 40 |
+ |
|
| 41 |
+#include <config.h> |
|
| 42 |
+#include "mt8365.dtsi" |
|
| 43 |
+#include "mt6357.dtsi" |
|
| 44 |
+ |
|
| 45 |
+/ {
|
|
| 46 |
+ model = "MT8365 SB35 board"; |
|
| 47 |
+ compatible = "mediatek,mt8365-sb35", "mediatek,mt8365"; |
|
| 48 |
+ |
|
| 49 |
+ memory@40000000 {
|
|
| 50 |
+ device_type = "memory"; |
|
| 51 |
+ reg = <0 0x40000000 0 0x40000000>; |
|
| 52 |
+ }; |
|
| 53 |
+ |
|
| 54 |
+ firmware: firmware {
|
|
| 55 |
+ optee {
|
|
| 56 |
+ compatible = "linaro,optee-tz"; |
|
| 57 |
+ method = "smc"; |
|
| 58 |
+ }; |
|
| 59 |
+ }; |
|
| 60 |
+ |
|
| 61 |
+ reserved-memory {
|
|
| 62 |
+ #address-cells = <2>; |
|
| 63 |
+ #size-cells = <2>; |
|
| 64 |
+ ranges; |
|
| 65 |
+ |
|
| 66 |
+ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
|
| 67 |
+ bl31_secmon_reserved: secmon@43000000 {
|
|
| 68 |
+ no-map; |
|
| 69 |
+ reg = <0 0x43000000 0 0x30000>; |
|
| 70 |
+ }; |
|
| 71 |
+ |
|
| 72 |
+ /* 12 MiB reserved for OP-TEE (BL32) |
|
| 73 |
+ * +-----------------------+ 0x43e0_0000 |
|
| 74 |
+ * | SHMEM 2MiB | |
|
| 75 |
+ * +-----------------------+ 0x43c0_0000 |
|
| 76 |
+ * | | TA_RAM 8MiB | |
|
| 77 |
+ * + TZDRAM +--------------+ 0x4340_0000 |
|
| 78 |
+ * | | TEE_RAM 2MiB | |
|
| 79 |
+ * +-----------------------+ 0x4320_0000 |
|
| 80 |
+ */ |
|
| 81 |
+ optee_reserved: optee@43200000 {
|
|
| 82 |
+ no-map; |
|
| 83 |
+ reg = <0 0x43200000 0 0x00c00000>; |
|
| 84 |
+ }; |
|
| 85 |
+ }; |
|
| 86 |
+ |
|
| 87 |
+ chosen {
|
|
| 88 |
+ stdout-path = &uart0; |
|
| 89 |
+ }; |
|
| 90 |
+}; |
|
| 91 |
+ |
|
| 92 |
+&uart0 {
|
|
| 93 |
+ status = "okay"; |
|
| 94 |
+}; |
|
| 95 |
+ |
|
| 96 |
+&mmc0 {
|
|
| 97 |
+ bus-width = <4>; |
|
| 98 |
+ max-frequency = <200000000>; |
|
| 99 |
+ cap-mmc-highspeed; |
|
| 100 |
+ mmc-hs200-1_8v; |
|
| 101 |
+ cap-mmc-hw-reset; |
|
| 102 |
+ vmmc-supply = <&mt6357_vemc_reg>; |
|
| 103 |
+ vqmmc-supply = <&mt6357_vio18_reg>; |
|
| 104 |
+ non-removable; |
|
| 105 |
+ status = "okay"; |
|
| 106 |
+}; |
|
| 107 |
+ |
|
| 108 |
+&usb {
|
|
| 109 |
+ status = "okay"; |
|
| 110 |
+}; |
|
| 111 |
+ |
|
| 112 |
+&ssusb {
|
|
| 113 |
+ mediatek,force-vbus; |
|
| 114 |
+ maximum-speed = "high-speed"; |
|
| 115 |
+ dr_mode = "peripheral"; |
|
| 116 |
+ status = "okay"; |
|
| 117 |
+}; |
|
| 118 |
+ |
|
| 119 |
+&dpi0 {
|
|
| 120 |
+ dpi_dual_edge; |
|
| 121 |
+ pinctrl-names = "default", "sleep"; |
|
| 122 |
+ pinctrl-0 = <&dpi_pin_func>; |
|
| 123 |
+ pinctrl-1 = <&dpi_pin_gpio>; |
|
| 124 |
+ status = "okay"; |
|
| 125 |
+}; |
|
| 126 |
+ |
|
| 127 |
+&i2c0 {
|
|
| 128 |
+ pinctrl-names = "default"; |
|
| 129 |
+ pinctrl-0 = <&i2c0_pins_default>; |
|
| 130 |
+ clock-frequency = <100000>; |
|
| 131 |
+ status = "okay"; |
|
| 132 |
+}; |
|
| 133 |
+ |
|
| 134 |
+&i2c1 {
|
|
| 135 |
+ pinctrl-names = "default"; |
|
| 136 |
+ pinctrl-0 = <&i2c1_pins_default>; |
|
| 137 |
+ clock-frequency = <100000>; |
|
| 138 |
+ status = "okay"; |
|
| 139 |
+ |
|
| 140 |
+ it66121hdmitx {
|
|
| 141 |
+ compatible = "ite,it66121"; |
|
| 142 |
+ reg = <0x4c>; |
|
| 143 |
+ pinctrl-names = "default"; |
|
| 144 |
+ pinctrl-0 = <&ite_pins_default>; |
|
| 145 |
+ vcn33-supply = <&mt6357_vcn33_bt_reg>; |
|
| 146 |
+ vcn18-supply = <&mt6357_vcn18_reg>; |
|
| 147 |
+ vrf12-supply = <&mt6357_vrf12_reg>; |
|
| 148 |
+ reset-gpios = <&gpio 69 GPIO_ACTIVE_LOW>; |
|
| 149 |
+ }; |
|
| 150 |
+}; |
|
| 151 |
+ |
|
| 152 |
+&i2c2 {
|
|
| 153 |
+ pinctrl-names = "default"; |
|
| 154 |
+ pinctrl-0 = <&i2c2_pins_default>; |
|
| 155 |
+ clock-frequency = <100000>; |
|
| 156 |
+ status = "okay"; |
|
| 157 |
+}; |
|
| 158 |
+ |
|
| 159 |
+&pio {
|
|
| 160 |
+ dpi_pin_func: dpi_pin_func {
|
|
| 161 |
+ function = "dpi"; |
|
| 162 |
+ groups = "dpi_enable"; |
|
| 163 |
+ }; |
|
| 164 |
+ |
|
| 165 |
+ dpi_pin_gpio: dpi_pin_gpio {
|
|
| 166 |
+ function = "dpi"; |
|
| 167 |
+ groups = "dpi_sleep"; |
|
| 168 |
+ }; |
|
| 169 |
+ |
|
| 170 |
+ i2c0_pins_default: i2c0_pins_default {
|
|
| 171 |
+ function = "i2c"; |
|
| 172 |
+ groups = "i2c0"; |
|
| 173 |
+ }; |
|
| 174 |
+ |
|
| 175 |
+ i2c1_pins_default: i2c1_pins_default {
|
|
| 176 |
+ function = "i2c"; |
|
| 177 |
+ groups = "i2c1"; |
|
| 178 |
+ }; |
|
| 179 |
+ |
|
| 180 |
+ i2c2_pins_default: i2c2_pins_default {
|
|
| 181 |
+ function = "i2c"; |
|
| 182 |
+ groups = "i2c2"; |
|
| 183 |
+ }; |
|
| 184 |
+ |
|
| 185 |
+ ite_pins_default: ite_pins_default {
|
|
| 186 |
+ pins_rst_ite {
|
|
| 187 |
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>; |
|
| 188 |
+ output-high; |
|
| 189 |
+ }; |
|
| 190 |
+ |
|
| 191 |
+ pins_irq_ite {
|
|
| 192 |
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>; |
|
| 193 |
+ input-enable; |
|
| 194 |
+ }; |
|
| 195 |
+ }; |
|
| 196 |
+}; |
|
| 197 |
diff --git a/configs/mt8365_sb35_defconfig b/configs/mt8365_sb35_defconfig |
|
| 198 |
new file mode 100644 |
|
| 199 |
index 0000000000..3c25705aab |
|
| 200 |
--- /dev/null |
|
| 201 |
+++ b/configs/mt8365_sb35_defconfig |
|
| 202 |
@@ -0,0 +1,97 @@ |
|
| 203 |
+CONFIG_ARM=y |
|
| 204 |
+CONFIG_COUNTER_FREQUENCY=13000000 |
|
| 205 |
+CONFIG_POSITION_INDEPENDENT=y |
|
| 206 |
+CONFIG_ARCH_MEDIATEK=y |
|
| 207 |
+CONFIG_SYS_TEXT_BASE=0x4c000000 |
|
| 208 |
+CONFIG_SYS_MALLOC_F_LEN=0x4000 |
|
| 209 |
+CONFIG_NR_DRAM_BANKS=1 |
|
| 210 |
+CONFIG_ENV_SIZE=0x1000 |
|
| 211 |
+CONFIG_ENV_OFFSET=0x0 |
|
| 212 |
+CONFIG_DM_GPIO=y |
|
| 213 |
+CONFIG_DEFAULT_DEVICE_TREE="mt8365-sb35" |
|
| 214 |
+CONFIG_TARGET_MT8365=y |
|
| 215 |
+CONFIG_DEBUG_UART_BASE=0x11002000 |
|
| 216 |
+CONFIG_DEBUG_UART_CLOCK=26000000 |
|
| 217 |
+CONFIG_SYS_LOAD_ADDR=0x4c000000 |
|
| 218 |
+CONFIG_DEBUG_UART=y |
|
| 219 |
+CONFIG_ENV_VARS_UBOOT_CONFIG=y |
|
| 220 |
+# CONFIG_ANDROID_BOOT_IMAGE is not set |
|
| 221 |
+CONFIG_FIT=y |
|
| 222 |
+CONFIG_FIT_SIGNATURE=y |
|
| 223 |
+CONFIG_USE_BOOTCOMMAND=y |
|
| 224 |
+CONFIG_BOOTCOMMAND="run distro_bootcmd" |
|
| 225 |
+CONFIG_DEFAULT_FDT_FILE="mt8365-sb35" |
|
| 226 |
+# CONFIG_DISPLAY_BOARDINFO is not set |
|
| 227 |
+CONFIG_HUSH_PARSER=y |
|
| 228 |
+# CONFIG_CMD_CONSOLE is not set |
|
| 229 |
+# CONFIG_CMD_BOOTD is not set |
|
| 230 |
+# CONFIG_CMD_ELF is not set |
|
| 231 |
+# CONFIG_CMD_GO is not set |
|
| 232 |
+# CONFIG_CMD_IMI is not set |
|
| 233 |
+# CONFIG_CMD_XIMG is not set |
|
| 234 |
+# CONFIG_CMD_CRC32 is not set |
|
| 235 |
+CONFIG_CMD_CLK=y |
|
| 236 |
+CONFIG_CMD_DFU=y |
|
| 237 |
+CONFIG_CMD_DM=y |
|
| 238 |
+CONFIG_CMD_GPT=y |
|
| 239 |
+# CONFIG_RANDOM_UUID is not set |
|
| 240 |
+CONFIG_CMD_I2C=y |
|
| 241 |
+# CONFIG_CMD_LOADB is not set |
|
| 242 |
+# CONFIG_CMD_LOADS is not set |
|
| 243 |
+CONFIG_CMD_MMC=y |
|
| 244 |
+CONFIG_CMD_PART=y |
|
| 245 |
+CONFIG_CMD_USB=y |
|
| 246 |
+CONFIG_CMD_USB_MASS_STORAGE=y |
|
| 247 |
+# CONFIG_CMD_ITEST is not set |
|
| 248 |
+CONFIG_CMD_DHCP=y |
|
| 249 |
+# CONFIG_CMD_BLOCK_CACHE is not set |
|
| 250 |
+CONFIG_CMD_SYSBOOT=y |
|
| 251 |
+CONFIG_CMD_EXT4=y |
|
| 252 |
+CONFIG_CMD_FAT=y |
|
| 253 |
+CONFIG_CMD_FS_GENERIC=y |
|
| 254 |
+CONFIG_ISO_PARTITION=y |
|
| 255 |
+CONFIG_ENV_IS_IN_MMC=y |
|
| 256 |
+CONFIG_SYS_MMC_ENV_PART=2 |
|
| 257 |
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
|
| 258 |
+CONFIG_ENV_IMPORT_FDT=y |
|
| 259 |
+CONFIG_DEVRES=y |
|
| 260 |
+CONFIG_CLK=y |
|
| 261 |
+CONFIG_DFU_MMC=y |
|
| 262 |
+CONFIG_USB_FUNCTION_FASTBOOT=y |
|
| 263 |
+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000 |
|
| 264 |
+CONFIG_FASTBOOT_BUF_SIZE=0x8000000 |
|
| 265 |
+CONFIG_FASTBOOT_FLASH=y |
|
| 266 |
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 |
|
| 267 |
+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y |
|
| 268 |
+CONFIG_DM_I2C=y |
|
| 269 |
+CONFIG_SYS_I2C_MTK=y |
|
| 270 |
+# CONFIG_INPUT is not set |
|
| 271 |
+# CONFIG_MMC_QUIRKS is not set |
|
| 272 |
+CONFIG_MMC_MTK=y |
|
| 273 |
+CONFIG_PHY=y |
|
| 274 |
+CONFIG_PHY_MTK_TPHY=y |
|
| 275 |
+CONFIG_PINCTRL=y |
|
| 276 |
+CONFIG_PINCONF=y |
|
| 277 |
+CONFIG_PINCTRL_MT8365=y |
|
| 278 |
+CONFIG_DM_RTC=y |
|
| 279 |
+CONFIG_RTC_EMULATION=y |
|
| 280 |
+CONFIG_BAUDRATE=921600 |
|
| 281 |
+CONFIG_DM_SERIAL=y |
|
| 282 |
+CONFIG_DEBUG_UART_ANNOUNCE=y |
|
| 283 |
+CONFIG_MTK_SERIAL=y |
|
| 284 |
+CONFIG_USB=y |
|
| 285 |
+CONFIG_DM_USB_GADGET=y |
|
| 286 |
+CONFIG_USB_XHCI_HCD=y |
|
| 287 |
+CONFIG_USB_XHCI_MTK=y |
|
| 288 |
+CONFIG_USB_MTU3=y |
|
| 289 |
+CONFIG_USB_STORAGE=y |
|
| 290 |
+CONFIG_USB_KEYBOARD=y |
|
| 291 |
+CONFIG_USB_HOST_ETHER=y |
|
| 292 |
+CONFIG_USB_GADGET=y |
|
| 293 |
+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d |
|
| 294 |
+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c |
|
| 295 |
+CONFIG_USB_ETHER=y |
|
| 296 |
+CONFIG_WDT=y |
|
| 297 |
+CONFIG_WDT_MTK=y |
|
| 298 |
+CONFIG_OF_LIBFDT_OVERLAY=y |
|
| 299 |
+CONFIG_LMB_MAX_REGIONS=16 |
|
| 300 |
-- |
|
| 301 |
2.25.1 |
|
| 302 | ||
| src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch 2024-05-07 15:01:53.574890872 +0800 | ||
|---|---|---|
| 1 |
From 6061bcfb8f1dfc47714beae179be4bc4e4223062 Mon Sep 17 00:00:00 2001 |
|
| 2 |
From: Rockefeller Lin <rockefeller.lin@innocomm.com> |
|
| 3 |
Date: Fri, 7 Apr 2023 03:29:44 +0000 |
|
| 4 |
Subject: [PATCH] Set bootdelay to 0 to save ~2secs of booting time |
|
| 5 | ||
| 6 |
Set bootdelay to 0 to save ~2secs of booting time |
|
| 7 |
--- |
|
| 8 |
configs/mt8365_sb35_defconfig | 1 + |
|
| 9 |
1 files changed, 1 insertions(+) |
|
| 10 | ||
| 11 |
diff --git a/configs/mt8365_sb35_defconfig b/configs/mt8365_sb35_defconfig |
|
| 12 |
index 204b97244b..ccf8c26892 100644 |
|
| 13 |
--- a/configs/mt8365_sb35_defconfig |
|
| 14 |
+++ b/configs/mt8365_sb35_defconfig |
|
| 15 |
@@ -96,3 +96,4 @@ CONFIG_WDT=y |
|
| 16 |
CONFIG_WDT_MTK=y |
|
| 17 |
CONFIG_OF_LIBFDT_OVERLAY=y |
|
| 18 |
CONFIG_LMB_MAX_REGIONS=16 |
|
| 19 |
+CONFIG_BOOTDELAY=0 |
|
| 20 |
-- |
|
| 21 |
2.25.1 |
|
| 22 | ||
| src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0002-Remove-DPI-and-it66121-from-sb35-dts.patch 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-bsp/u-boot/files/0002-Remove-DPI-and-it66121-from-sb35-dts.patch 2024-05-07 15:01:53.574890872 +0800 | ||
|---|---|---|
| 1 |
From 29ec664a6ac95151a2967527c1a9d04603aa62c3 Mon Sep 17 00:00:00 2001 |
|
| 2 |
From: Rockefeller Lin <rockefeller.lin@innocomm.com> |
|
| 3 |
Date: Wed, 24 May 2023 12:57:31 +0800 |
|
| 4 |
Subject: [PATCH 1/1] Remove DPI and it66121 from sb35 dts |
|
| 5 | ||
| 6 |
The HDMI bridge on SB35 EVK is lt9611 and interface is DSI, so remove |
|
| 7 |
DPI and it66121 nodes. |
|
| 8 | ||
| 9 |
The lt9611 node is added but disable it because MTK DSI is still not supported yet. |
|
| 10 |
--- |
|
| 11 |
arch/arm/dts/mt8365-sb35.dts | 66 +++++++++++++++++++----------------- |
|
| 12 |
1 file changed, 35 insertions(+), 31 deletions(-) |
|
| 13 | ||
| 14 |
diff --git a/arch/arm/dts/mt8365-sb35.dts b/arch/arm/dts/mt8365-sb35.dts |
|
| 15 |
index 5f57657026..b645d276a6 100644 |
|
| 16 |
--- a/arch/arm/dts/mt8365-sb35.dts |
|
| 17 |
+++ b/arch/arm/dts/mt8365-sb35.dts |
|
| 18 |
@@ -84,14 +84,6 @@ |
|
| 19 |
status = "okay"; |
|
| 20 |
}; |
|
| 21 |
|
|
| 22 |
-&dpi0 {
|
|
| 23 |
- dpi_dual_edge; |
|
| 24 |
- pinctrl-names = "default", "sleep"; |
|
| 25 |
- pinctrl-0 = <&dpi_pin_func>; |
|
| 26 |
- pinctrl-1 = <&dpi_pin_gpio>; |
|
| 27 |
- status = "okay"; |
|
| 28 |
-}; |
|
| 29 |
- |
|
| 30 |
&i2c0 {
|
|
| 31 |
pinctrl-names = "default"; |
|
| 32 |
pinctrl-0 = <&i2c0_pins_default>; |
|
| 33 |
@@ -105,16 +97,15 @@ |
|
| 34 |
clock-frequency = <100000>; |
|
| 35 |
status = "okay"; |
|
| 36 |
|
|
| 37 |
- it66121hdmitx {
|
|
| 38 |
- compatible = "ite,it66121"; |
|
| 39 |
+#if 0 |
|
| 40 |
+ lt9611hdmitx {
|
|
| 41 |
+ compatible = "lontium,lt9611"; |
|
| 42 |
reg = <0x4c>; |
|
| 43 |
pinctrl-names = "default"; |
|
| 44 |
- pinctrl-0 = <&ite_pins_default>; |
|
| 45 |
- vcn33-supply = <&mt6357_vcn33_bt_reg>; |
|
| 46 |
- vcn18-supply = <&mt6357_vcn18_reg>; |
|
| 47 |
- vrf12-supply = <&mt6357_vrf12_reg>; |
|
| 48 |
- reset-gpios = <&gpio 69 GPIO_ACTIVE_LOW>; |
|
| 49 |
+ pinctrl-0 = <&hdmi_pins_default>; |
|
| 50 |
+ reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>; |
|
| 51 |
}; |
|
| 52 |
+#endif |
|
| 53 |
}; |
|
| 54 |
|
|
| 55 |
&i2c2 {
|
|
| 56 |
@@ -125,16 +116,6 @@ |
|
| 57 |
}; |
|
| 58 |
|
|
| 59 |
&pio {
|
|
| 60 |
- dpi_pin_func: dpi_pin_func {
|
|
| 61 |
- function = "dpi"; |
|
| 62 |
- groups = "dpi_enable"; |
|
| 63 |
- }; |
|
| 64 |
- |
|
| 65 |
- dpi_pin_gpio: dpi_pin_gpio {
|
|
| 66 |
- function = "dpi"; |
|
| 67 |
- groups = "dpi_sleep"; |
|
| 68 |
- }; |
|
| 69 |
- |
|
| 70 |
i2c0_pins_default: i2c0_pins_default {
|
|
| 71 |
function = "i2c"; |
|
| 72 |
groups = "i2c0"; |
|
| 73 |
@@ -150,15 +131,38 @@ |
|
| 74 |
groups = "i2c2"; |
|
| 75 |
}; |
|
| 76 |
|
|
| 77 |
- ite_pins_default: ite_pins_default {
|
|
| 78 |
- pins_rst_ite {
|
|
| 79 |
- pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>; |
|
| 80 |
- output-high; |
|
| 81 |
+#if 0 |
|
| 82 |
+ hdmi_pins_default: hdmi_pins_default {
|
|
| 83 |
+ pin_pwr_en {
|
|
| 84 |
+ pinmux = <MT8365_PIN_4_GPIO4__FUNC_GPIO4>; |
|
| 85 |
+ output-low; |
|
| 86 |
}; |
|
| 87 |
|
|
| 88 |
- pins_irq_ite {
|
|
| 89 |
- pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>; |
|
| 90 |
+ pin_lt9611_1v8_en {
|
|
| 91 |
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_GPIO19>; |
|
| 92 |
+ output-low; |
|
| 93 |
+ }; |
|
| 94 |
+ |
|
| 95 |
+ pin_lt9611_rst {
|
|
| 96 |
+ pinmux = <MT8365_PIN_20_LCM_RST__FUNC_GPIO20>; |
|
| 97 |
+ output-low; |
|
| 98 |
+ }; |
|
| 99 |
+ |
|
| 100 |
+ pin_lt9611_3v3_en {
|
|
| 101 |
+ pinmux = <MT8365_PIN_21_DSI_TE__FUNC_GPIO21>; |
|
| 102 |
+ output-low; |
|
| 103 |
+ }; |
|
| 104 |
+ |
|
| 105 |
+ pin_lt9611_intr {
|
|
| 106 |
+ pinmux = <MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125>; |
|
| 107 |
input-enable; |
|
| 108 |
+ bias-pull-up; |
|
| 109 |
+ }; |
|
| 110 |
+ |
|
| 111 |
+ pin_dsi_sel {
|
|
| 112 |
+ pinmux = <MT8365_PIN_2_GPIO2__FUNC_GPIO2>; |
|
| 113 |
+ output-low; |
|
| 114 |
}; |
|
| 115 |
}; |
|
| 116 |
+#endif |
|
| 117 |
}; |
|
| 118 |
-- |
|
| 119 |
2.25.1 |
|
| 120 | ||
| src/meta-mediatek-bsp/recipes-bsp/u-boot/files/fw_env.config 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-bsp/u-boot/files/fw_env.config 2024-05-07 15:01:53.574890872 +0800 | ||
|---|---|---|
| 1 |
# Configuration file for fw_(printenv/setenv) utility. |
|
| 2 |
# Up to two entries are valid, in this case the redundant |
|
| 3 |
# environment sector is assumed present. |
|
| 4 |
# Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash. |
|
| 5 |
# Futhermore, if the Flash sector size is omitted, this value is assumed to |
|
| 6 |
# be the same as the Environment size, which is valid for NOR and SPI-dataflash |
|
| 7 |
# Device offset must be prefixed with 0x to be parsed as a hexadecimal value. |
|
| 8 | ||
| 9 |
# NOR example |
|
| 10 |
# MTD device name Device offset Env. size Flash sector size Number of sectors |
|
| 11 |
#/dev/mtd1 0x0000 0x4000 0x4000 |
|
| 12 |
#/dev/mtd2 0x0000 0x4000 0x4000 |
|
| 13 | ||
| 14 |
# MTD SPI-dataflash example |
|
| 15 |
# MTD device name Device offset Env. size Flash sector size Number of sectors |
|
| 16 |
#/dev/mtd5 0x4200 0x4200 |
|
| 17 |
#/dev/mtd6 0x4200 0x4200 |
|
| 18 | ||
| 19 |
# NAND example |
|
| 20 |
#/dev/mtd0 0x4000 0x4000 0x20000 2 |
|
| 21 | ||
| 22 |
# On a block device a negative offset is treated as a backwards offset from the |
|
| 23 |
# end of the device/partition, rather than a forwards offset from the start. |
|
| 24 | ||
| 25 |
# Block device example |
|
| 26 |
/dev/mmcblk0boot1 0x0000 0x1000 |
|
| 27 |
# /dev/mmcblk0boot1 -0x1000 0x1000 |
|
| 28 | ||
| 29 |
# VFAT example |
|
| 30 |
#/boot/uboot.env 0x0000 0x4000 |
|
| 31 | ||
| 32 |
# UBI volume |
|
| 33 |
#/dev/ubi0_0 0x0 0x1f000 0x1f000 |
|
| 34 |
#/dev/ubi0_1 0x0 0x1f000 0x1f000 |
|
| 35 | ||
| 36 |
# UBI volume by name |
|
| 37 |
#/dev/ubi0:env 0x0 0x1f000 0x1f000 |
|
| 38 |
#/dev/ubi0:env-redund 0x0 0x1f000 0x1f000 |
|
| src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb 2024-05-07 15:25:40.814613659 +0800 → src/meta-mediatek-bsp/recipes-bsp/u-boot/u-boot_git.bb 2024-05-07 15:05:16.603695600 +0800 | ||
|---|---|---|
| 5 | 5 |
file://0001-Revert-cmd-pxe_utils-Check-fdtcontroladdr-in-label_b.patch \ |
| 6 | 6 |
file://fw_env-mmc-boot.config \ |
| 7 | 7 |
file://fw_env-ufs-boot.config \ |
| 8 |
file://0001-Add-dedicated-sb35-defconfig-and-dts-files.patch \ |
|
| 9 |
file://0002-Remove-DPI-and-it66121-from-sb35-dts.patch \ |
|
| 10 |
file://0001-Set-bootdelay-to-0-to-save-2secs-of-booting-time.patch \ |
|
| 8 | 11 |
" |
| 9 | 12 | |
| 10 | 13 |
python() {
|
| src/meta-mediatek-bsp/recipes-kernel/dtbo/dtbo.bb 2024-05-07 15:25:40.818613720 +0800 → src/meta-mediatek-bsp/recipes-kernel/dtbo/dtbo.bb 2024-05-07 15:08:33.081422800 +0800 | ||
|---|---|---|
| 110 | 110 | |
| 111 | 111 |
SRC_URI:append:mt8365-sb35 = " \ |
| 112 | 112 |
file://panel-raspberrypi.dts \ |
| 113 |
file://rs232.dts \ |
|
| 114 |
file://spidev.dts \ |
|
| 113 | 115 |
" |
| 114 | 116 | |
| 115 | 117 |
SRC_URI:append:mt8516-pumpkin = " \ |
| src/meta-mediatek-bsp/recipes-kernel/dtbo/mt8365-sb35/rs232.dts 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-kernel/dtbo/mt8365-sb35/rs232.dts 2024-05-07 09:58:21.262013800 +0800 | ||
|---|---|---|
| 1 |
/dts-v1/; |
|
| 2 |
/plugin/; |
|
| 3 | ||
| 4 |
#include <dt-bindings/gpio/gpio.h> |
|
| 5 |
#include <dt-bindings/pinctrl/mt8365-pinfunc.h> |
|
| 6 | ||
| 7 |
/ {
|
|
| 8 |
fragment@0 {
|
|
| 9 |
target = <&pio>; |
|
| 10 |
__overlay__ {
|
|
| 11 |
rs232_pins: rs232-pins {
|
|
| 12 |
pins_rx {
|
|
| 13 |
pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>; |
|
| 14 |
input-enable; |
|
| 15 |
bias-pull-up; |
|
| 16 |
}; |
|
| 17 |
pins_tx_cts_rts {
|
|
| 18 |
pinmux = <MT8365_PIN_38_UTXD1__FUNC_UTXD1>, |
|
| 19 |
<MT8365_PIN_39_URXD2__FUNC_UCTS1>, |
|
| 20 |
<MT8365_PIN_40_UTXD2__FUNC_URTS1>; |
|
| 21 |
}; |
|
| 22 |
pins_rs232_shdn {
|
|
| 23 |
pinmux = <MT8365_PIN_10_GPIO10__FUNC_GPIO10>; |
|
| 24 |
output-high; |
|
| 25 |
}; |
|
| 26 |
pins_rs232_en {
|
|
| 27 |
pinmux = <MT8365_PIN_8_GPIO8__FUNC_GPIO8>; |
|
| 28 |
output-high; |
|
| 29 |
}; |
|
| 30 |
}; |
|
| 31 |
}; |
|
| 32 |
}; |
|
| 33 | ||
| 34 |
fragment@1 {
|
|
| 35 |
target = <&uart1>; |
|
| 36 |
__overlay__ {
|
|
| 37 |
pinctrl-0 = <&rs232_pins>; |
|
| 38 |
pinctrl-names = "default"; |
|
| 39 |
status = "okay"; |
|
| 40 |
}; |
|
| 41 |
}; |
|
| 42 |
}; |
|
| src/meta-mediatek-bsp/recipes-kernel/dtbo/mt8365-sb35/spidev.dts 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-kernel/dtbo/mt8365-sb35/spidev.dts 2024-05-07 09:58:21.262013800 +0800 | ||
|---|---|---|
| 1 |
/dts-v1/; |
|
| 2 |
/plugin/; |
|
| 3 | ||
| 4 |
#include <dt-bindings/gpio/gpio.h> |
|
| 5 |
#include <dt-bindings/pinctrl/mt8365-pinfunc.h> |
|
| 6 | ||
| 7 |
/ {
|
|
| 8 |
fragment@0 {
|
|
| 9 |
target = <&pio>; |
|
| 10 |
__overlay__ {
|
|
| 11 |
spi_pins: spi-pins {
|
|
| 12 |
pins {
|
|
| 13 |
pinmux = <MT8365_PIN_9_GPIO9__FUNC_SPI_CSB>, |
|
| 14 |
<MT8365_PIN_10_GPIO10__FUNC_SPI_MI>; |
|
| 15 |
bias-disable; |
|
| 16 |
}; |
|
| 17 |
out_pins {
|
|
| 18 |
pinmux = <MT8365_PIN_8_GPIO8__FUNC_SPI_CLK>, |
|
| 19 |
<MT8365_PIN_11_GPIO11__FUNC_SPI_MO>; |
|
| 20 |
bias-disable; |
|
| 21 |
drive-strength = <MTK_DRIVE_6mA>; |
|
| 22 |
}; |
|
| 23 |
}; |
|
| 24 |
}; |
|
| 25 |
}; |
|
| 26 | ||
| 27 |
fragment@1 {
|
|
| 28 |
target = <&spi>; |
|
| 29 |
__overlay__ {
|
|
| 30 |
pinctrl-0 = <&spi_pins>; |
|
| 31 |
pinctrl-names = "default"; |
|
| 32 |
mediatek,pad-select = <0>; |
|
| 33 |
status = "okay"; |
|
| 34 | ||
| 35 |
spidev@0 {
|
|
| 36 |
compatible = "mediatek,aiot-board"; |
|
| 37 |
spi-max-frequency = <50000000>; |
|
| 38 |
reg = <0>; |
|
| 39 |
}; |
|
| 40 |
}; |
|
| 41 |
}; |
|
| 42 |
}; |
|
| src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0003-Patch-for-v23.2-Linux-MTK-kernel.patch 1970-01-01 08:00:00.000000000 +0800 → src/meta-mediatek-bsp/recipes-kernel/linux/linux-mtk/0003-Patch-for-v23.2-Linux-MTK-kernel.patch 2024-05-09 11:16:43.960867421 +0800 | ||
|---|---|---|
| 1 |
From 51ada95713086d19d5d8153d117f1982887595d8 Mon Sep 17 00:00:00 2001 |
|
| 2 |
From: lion6230i <lion6230i@gmail.com> |
|
| 3 |
Date: Thu, 9 May 2024 11:12:16 +0800 |
|
| 4 |
Subject: [PATCH] Patch for v23.2 Linux MTK kernel. |
|
| 5 | ||
| 6 |
--- |
|
| 7 |
arch/arm64/boot/dts/mediatek/mt8365-sb35.dts | 87 +- |
|
| 8 |
drivers/gpu/drm/bridge/lontium-lt9611.c | 343 +- |
|
| 9 |
drivers/gpu/drm/mediatek/mtk_dsi.c | 197 +- |
|
| 10 |
.../drm/panel/panel-rpi-pumpkin-touchscreen.c | 4 +- |
|
| 11 |
drivers/spi/spi-mt65xx.c | 2 +- |
|
| 12 |
sound/soc/codecs/Kconfig | 5 + |
|
| 13 |
sound/soc/codecs/Makefile | 3 + |
|
| 14 |
sound/soc/codecs/rt5509.c | 3513 +++++++++++++++++ |
|
| 15 |
sound/soc/codecs/rt5509.h | 488 +++ |
|
| 16 |
sound/soc/mediatek/mt8365/mt8365-sb35.c | 42 +- |
|
| 17 |
10 files changed, 4345 insertions(+), 339 deletions(-) |
|
| 18 |
create mode 100644 sound/soc/codecs/rt5509.c |
|
| 19 |
create mode 100644 sound/soc/codecs/rt5509.h |
|
| 20 | ||
| 21 |
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts |
|
| 22 |
index 8b7442bafa32..52b3fa4357da 100644 |
|
| 23 |
--- a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts |
|
| 24 |
+++ b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts |
|
| 25 |
@@ -74,6 +74,20 @@ sound: sound {
|
|
| 26 |
pinctrl-4 = <&aud_pins_default>; |
|
| 27 |
pinctrl-5 = <&aud_pins_dmic>; |
|
| 28 |
status = "okay"; |
|
| 29 |
+ |
|
| 30 |
+ dai-link@0 {
|
|
| 31 |
+ dai-link-name = "2ND I2S BE"; |
|
| 32 |
+ codec {
|
|
| 33 |
+ sound-dai = <&speaker_amp_left>; |
|
| 34 |
+ }; |
|
| 35 |
+ }; |
|
| 36 |
+ |
|
| 37 |
+ dai-link@1 {
|
|
| 38 |
+ dai-link-name = "2ND I2S BE 2"; |
|
| 39 |
+ codec {
|
|
| 40 |
+ sound-dai = <&speaker_amp_right>; |
|
| 41 |
+ }; |
|
| 42 |
+ }; |
|
| 43 |
}; |
|
| 44 |
|
|
| 45 |
reserved-memory {
|
|
| 46 |
@@ -94,6 +108,14 @@ optee_reserved: optee@43200000 {
|
|
| 47 |
no-map; |
|
| 48 |
reg = <0 0x43200000 0 0x00c00000>; |
|
| 49 |
}; |
|
| 50 |
+ |
|
| 51 |
+ /* global autoconfigured region for contiguous allocations */ |
|
| 52 |
+ linux,cma {
|
|
| 53 |
+ compatible = "shared-dma-pool"; |
|
| 54 |
+ reusable; |
|
| 55 |
+ size = <0x00000000 0x01c00000>; |
|
| 56 |
+ linux,cma-default; |
|
| 57 |
+ }; |
|
| 58 |
}; |
|
| 59 |
|
|
| 60 |
dc5v: dc5v-regulator {
|
|
| 61 |
@@ -163,6 +185,9 @@ hdmi-out {
|
|
| 62 |
compatible = "hdmi-connector"; |
|
| 63 |
type = "a"; |
|
| 64 |
ddc-i2c-bus = <&i2c2>; |
|
| 65 |
+ pinctrl-0 = <&hdmi_ddc_pins>; |
|
| 66 |
+ pinctrl-names = "default"; |
|
| 67 |
+ ddc-en-gpios = <&pio 4 GPIO_ACTIVE_HIGH>; |
|
| 68 |
|
|
| 69 |
port {
|
|
| 70 |
hdmi_con: endpoint {
|
|
| 71 |
@@ -299,21 +324,27 @@ &i2c1 {
|
|
| 72 |
clock-frequency = <100000>; |
|
| 73 |
status = "okay"; |
|
| 74 |
|
|
| 75 |
- rt5509_left: codec@34 {
|
|
| 76 |
- compatible = "realtek,rt5514"; |
|
| 77 |
+ speaker_amp_left:speaker_amp@34 {
|
|
| 78 |
+ compatible = "richtek,rt5509"; |
|
| 79 |
reg = <0x34>; |
|
| 80 |
+ status = "okay"; |
|
| 81 |
+ #sound-dai-cells = <0>; |
|
| 82 |
+ rt5509,lrs = "left"; |
|
| 83 |
}; |
|
| 84 |
|
|
| 85 |
- rt5509_right: codec@35 {
|
|
| 86 |
- compatible = "realtek,rt5514"; |
|
| 87 |
+ speaker_amp_right:speaker_amp@35 {
|
|
| 88 |
+ compatible = "richtek,rt5509"; |
|
| 89 |
reg = <0x35>; |
|
| 90 |
+ status = "okay"; |
|
| 91 |
+ #sound-dai-cells = <0>; |
|
| 92 |
+ rt5509,lrs = "right"; |
|
| 93 |
}; |
|
| 94 |
|
|
| 95 |
hdmi-bridge@3b {
|
|
| 96 |
compatible = "lontium,lt9611"; |
|
| 97 |
reg = <0x3b>; |
|
| 98 |
pinctrl-0 = <&hdmi_pins>; |
|
| 99 |
- pintctrl-names = "default"; |
|
| 100 |
+ pinctrl-names = "default"; |
|
| 101 |
|
|
| 102 |
reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; |
|
| 103 |
interrupts-extended = <&pio 125 IRQ_TYPE_EDGE_FALLING>; |
|
| 104 |
@@ -576,8 +607,9 @@ i2c0_pins: i2c0 {
|
|
| 105 |
pins_i2c {
|
|
| 106 |
pinmux = <MT8365_PIN_57_SDA0__FUNC_SDA0_0>, |
|
| 107 |
<MT8365_PIN_58_SCL0__FUNC_SCL0_0>; |
|
| 108 |
- mediatek,pull-up-adv = <3>; |
|
| 109 |
- mediatek,drive-strength-adv = <7>; |
|
| 110 |
+ //mediatek,pull-up-adv = <3>; |
|
| 111 |
+ //mediatek,drive-strength-adv = <7>; |
|
| 112 |
+ bias-pull-up; |
|
| 113 |
}; |
|
| 114 |
}; |
|
| 115 |
|
|
| 116 |
@@ -596,8 +628,9 @@ i2c2_pins: i2c2 {
|
|
| 117 |
pins_i2c {
|
|
| 118 |
pinmux = <MT8365_PIN_61_SDA2__FUNC_SDA2_0>, |
|
| 119 |
<MT8365_PIN_62_SCL2__FUNC_SCL2_0>; |
|
| 120 |
- mediatek,pull-up-adv = <3>; |
|
| 121 |
- mediatek,drive-strength-adv = <00>; |
|
| 122 |
+ //mediatek,pull-up-adv = <3>; |
|
| 123 |
+ //mediatek,drive-strength-adv = <00>; |
|
| 124 |
+ bias-pull-up; |
|
| 125 |
}; |
|
| 126 |
}; |
|
| 127 |
|
|
| 128 |
@@ -605,8 +638,9 @@ i2c3_pins: i2c3 {
|
|
| 129 |
pins_i2c {
|
|
| 130 |
pinmux = <MT8365_PIN_63_SDA3__FUNC_SDA3_0>, |
|
| 131 |
<MT8365_PIN_64_SCL3__FUNC_SCL3_0>; |
|
| 132 |
- mediatek,pull-up-adv = <3>; |
|
| 133 |
- mediatek,drive-strength-adv = <00>; |
|
| 134 |
+ //mediatek,pull-up-adv = <3>; |
|
| 135 |
+ //mediatek,drive-strength-adv = <00>; |
|
| 136 |
+ bias-pull-up; |
|
| 137 |
}; |
|
| 138 |
}; |
|
| 139 |
|
|
| 140 |
@@ -641,13 +675,42 @@ pin_ethernet_reset {
|
|
| 141 |
}; |
|
| 142 |
}; |
|
| 143 |
|
|
| 144 |
- hdmi_pins: hdmi-pins {
|
|
| 145 |
+ hdmi_ddc_pins: hdmi-ddc-pins {
|
|
| 146 |
pin_pwr_en {
|
|
| 147 |
pinmux = <MT8365_PIN_4_GPIO4__FUNC_GPIO4>; |
|
| 148 |
output-high; |
|
| 149 |
}; |
|
| 150 |
}; |
|
| 151 |
|
|
| 152 |
+ |
|
| 153 |
+ hdmi_pins: hdmi-pins {
|
|
| 154 |
+ pin_lt9611_1v8_en {
|
|
| 155 |
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_GPIO19>; |
|
| 156 |
+ output-low; |
|
| 157 |
+ }; |
|
| 158 |
+ |
|
| 159 |
+ pin_lt9611_rst {
|
|
| 160 |
+ pinmux = <MT8365_PIN_20_LCM_RST__FUNC_GPIO20>; |
|
| 161 |
+ output-low; |
|
| 162 |
+ }; |
|
| 163 |
+ |
|
| 164 |
+ pin_lt9611_3v3_en {
|
|
| 165 |
+ pinmux = <MT8365_PIN_21_DSI_TE__FUNC_GPIO21>; |
|
| 166 |
+ output-low; |
|
| 167 |
+ }; |
|
| 168 |
+ |
|
| 169 |
+ pin_lt9611_intr {
|
|
| 170 |
+ pinmux = <MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125>; |
|
| 171 |
+ input-enable; |
|
| 172 |
+ bias-pull-up; |
|
| 173 |
+ }; |
|
| 174 |
+ |
|
| 175 |
+ pin_dsi_sel {
|
|
| 176 |
+ pinmux = <MT8365_PIN_2_GPIO2__FUNC_GPIO2>; |
|
| 177 |
+ output-low; |
|
| 178 |
+ }; |
|
| 179 |
+ }; |
|
| 180 |
+ |
|
| 181 |
keypad_pins: keypad-pins {
|
|
| 182 |
pins_cols {
|
|
| 183 |
pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>, |
|
| 184 |
diff --git a/drivers/gpu/drm/bridge/lontium-lt9611.c b/drivers/gpu/drm/bridge/lontium-lt9611.c |
|
| 185 |
index 29b1ce2140ab..cb70b7737889 100644 |
|
| 186 |
--- a/drivers/gpu/drm/bridge/lontium-lt9611.c |
|
| 187 |
+++ b/drivers/gpu/drm/bridge/lontium-lt9611.c |
|
| 188 |
@@ -17,6 +17,7 @@ |
|
| 189 |
#include <drm/drm_atomic_helper.h> |
|
| 190 |
#include <drm/drm_bridge.h> |
|
| 191 |
#include <drm/drm_mipi_dsi.h> |
|
| 192 |
+#include <drm/drm_of.h> |
|
| 193 |
#include <drm/drm_print.h> |
|
| 194 |
#include <drm/drm_probe_helper.h> |
|
| 195 |
|
|
| 196 |
@@ -31,7 +32,7 @@ |
|
| 197 |
struct lt9611 {
|
|
| 198 |
struct device *dev; |
|
| 199 |
struct drm_bridge bridge; |
|
| 200 |
- struct drm_connector connector; |
|
| 201 |
+ struct drm_bridge *next_bridge; |
|
| 202 |
|
|
| 203 |
struct regmap *regmap; |
|
| 204 |
|
|
| 205 |
@@ -56,7 +57,6 @@ struct lt9611 {
|
|
| 206 |
enum drm_connector_status status; |
|
| 207 |
|
|
| 208 |
u8 edid_buf[EDID_SEG_SIZE]; |
|
| 209 |
- u32 vic; |
|
| 210 |
}; |
|
| 211 |
|
|
| 212 |
#define LT9611_PAGE_CONTROL 0xff |
|
| 213 |
@@ -82,34 +82,11 @@ static const struct regmap_config lt9611_regmap_config = {
|
|
| 214 |
.num_ranges = ARRAY_SIZE(lt9611_ranges), |
|
| 215 |
}; |
|
| 216 |
|
|
| 217 |
-struct lt9611_mode {
|
|
| 218 |
- u16 hdisplay; |
|
| 219 |
- u16 vdisplay; |
|
| 220 |
- u8 vrefresh; |
|
| 221 |
- u8 lanes; |
|
| 222 |
- u8 intfs; |
|
| 223 |
-}; |
|
| 224 |
- |
|
| 225 |
-static struct lt9611_mode lt9611_modes[] = {
|
|
| 226 |
- { 3840, 2160, 30, 4, 2 }, /* 3840x2160 24bit 30Hz 4Lane 2ports */
|
|
| 227 |
- { 1920, 1080, 60, 4, 1 }, /* 1080P 24bit 60Hz 4lane 1port */
|
|
| 228 |
- { 1920, 1080, 30, 3, 1 }, /* 1080P 24bit 30Hz 3lane 1port */
|
|
| 229 |
- { 1920, 1080, 24, 3, 1 },
|
|
| 230 |
- { 720, 480, 60, 4, 1 },
|
|
| 231 |
- { 720, 576, 50, 2, 1 },
|
|
| 232 |
- { 640, 480, 60, 2, 1 },
|
|
| 233 |
-}; |
|
| 234 |
- |
|
| 235 |
static struct lt9611 *bridge_to_lt9611(struct drm_bridge *bridge) |
|
| 236 |
{
|
|
| 237 |
return container_of(bridge, struct lt9611, bridge); |
|
| 238 |
} |
|
| 239 |
|
|
| 240 |
-static struct lt9611 *connector_to_lt9611(struct drm_connector *connector) |
|
| 241 |
-{
|
|
| 242 |
- return container_of(connector, struct lt9611, connector); |
|
| 243 |
-} |
|
| 244 |
- |
|
| 245 |
static int lt9611_mipi_input_analog(struct lt9611 *lt9611) |
|
| 246 |
{
|
|
| 247 |
const struct reg_sequence reg_cfg[] = {
|
|
| 248 |
@@ -157,12 +134,12 @@ static void lt9611_mipi_video_setup(struct lt9611 *lt9611, |
|
| 249 |
hactive = mode->hdisplay; |
|
| 250 |
hsync_len = mode->hsync_end - mode->hsync_start; |
|
| 251 |
hfront_porch = mode->hsync_start - mode->hdisplay; |
|
| 252 |
- hsync_porch = hsync_len + mode->htotal - mode->hsync_end; |
|
| 253 |
+ hsync_porch = mode->htotal - mode->hsync_start; |
|
| 254 |
|
|
| 255 |
vactive = mode->vdisplay; |
|
| 256 |
vsync_len = mode->vsync_end - mode->vsync_start; |
|
| 257 |
vfront_porch = mode->vsync_start - mode->vdisplay; |
|
| 258 |
- vsync_porch = vsync_len + mode->vtotal - mode->vsync_end; |
|
| 259 |
+ vsync_porch = mode->vtotal - mode->vsync_start; |
|
| 260 |
|
|
| 261 |
regmap_write(lt9611->regmap, 0x830d, (u8)(v_total / 256)); |
|
| 262 |
regmap_write(lt9611->regmap, 0x830e, (u8)(v_total % 256)); |
|
| 263 |
@@ -185,12 +162,14 @@ static void lt9611_mipi_video_setup(struct lt9611 *lt9611, |
|
| 264 |
|
|
| 265 |
regmap_write(lt9611->regmap, 0x8319, (u8)(hfront_porch % 256)); |
|
| 266 |
|
|
| 267 |
- regmap_write(lt9611->regmap, 0x831a, (u8)(hsync_porch / 256)); |
|
| 268 |
+ regmap_write(lt9611->regmap, 0x831a, (u8)(hsync_porch / 256) | |
|
| 269 |
+ ((hfront_porch / 256) << 4)); |
|
| 270 |
regmap_write(lt9611->regmap, 0x831b, (u8)(hsync_porch % 256)); |
|
| 271 |
} |
|
| 272 |
|
|
| 273 |
-static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode) |
|
| 274 |
+static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) |
|
| 275 |
{
|
|
| 276 |
+ unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; |
|
| 277 |
const struct reg_sequence reg_cfg[] = {
|
|
| 278 |
{ 0x830b, 0x01 },
|
|
| 279 |
{ 0x830c, 0x10 },
|
|
| 280 |
@@ -205,7 +184,6 @@ static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mod |
|
| 281 |
|
|
| 282 |
/* stage 2 */ |
|
| 283 |
{ 0x834a, 0x40 },
|
|
| 284 |
- { 0x831d, 0x10 },
|
|
| 285 |
|
|
| 286 |
/* MK limit */ |
|
| 287 |
{ 0x832d, 0x38 },
|
|
| 288 |
@@ -220,30 +198,28 @@ static void lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mod |
|
| 289 |
{ 0x8325, 0x00 },
|
|
| 290 |
{ 0x832a, 0x01 },
|
|
| 291 |
{ 0x834a, 0x10 },
|
|
| 292 |
- { 0x831d, 0x10 },
|
|
| 293 |
- { 0x8326, 0x37 },
|
|
| 294 |
}; |
|
| 295 |
+ u8 pol = 0x10; |
|
| 296 |
|
|
| 297 |
- regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); |
|
| 298 |
+ if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
|
| 299 |
+ pol |= 0x2; |
|
| 300 |
+ if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
|
| 301 |
+ pol |= 0x1; |
|
| 302 |
+ regmap_write(lt9611->regmap, 0x831d, pol); |
|
| 303 |
|
|
| 304 |
- switch (mode->hdisplay) {
|
|
| 305 |
- case 640: |
|
| 306 |
- regmap_write(lt9611->regmap, 0x8326, 0x14); |
|
| 307 |
- break; |
|
| 308 |
- case 1920: |
|
| 309 |
- regmap_write(lt9611->regmap, 0x8326, 0x37); |
|
| 310 |
- break; |
|
| 311 |
- case 3840: |
|
| 312 |
+ if (mode->hdisplay == 3840) |
|
| 313 |
regmap_multi_reg_write(lt9611->regmap, reg_cfg2, ARRAY_SIZE(reg_cfg2)); |
|
| 314 |
- break; |
|
| 315 |
- } |
|
| 316 |
+ else |
|
| 317 |
+ regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); |
|
| 318 |
+ |
|
| 319 |
+ regmap_write(lt9611->regmap, 0x8326, pcr_m); |
|
| 320 |
|
|
| 321 |
/* pcr rst */ |
|
| 322 |
regmap_write(lt9611->regmap, 0x8011, 0x5a); |
|
| 323 |
regmap_write(lt9611->regmap, 0x8011, 0xfa); |
|
| 324 |
} |
|
| 325 |
|
|
| 326 |
-static int lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode) |
|
| 327 |
+static int lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) |
|
| 328 |
{
|
|
| 329 |
unsigned int pclk = mode->clock; |
|
| 330 |
const struct reg_sequence reg_cfg[] = {
|
|
| 331 |
@@ -257,16 +233,21 @@ static int lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode |
|
| 332 |
{ 0x8126, 0x55 },
|
|
| 333 |
{ 0x8127, 0x66 },
|
|
| 334 |
{ 0x8128, 0x88 },
|
|
| 335 |
+ { 0x812a, 0x20 },
|
|
| 336 |
}; |
|
| 337 |
|
|
| 338 |
regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); |
|
| 339 |
|
|
| 340 |
- if (pclk > 150000) |
|
| 341 |
+ if (pclk > 150000) {
|
|
| 342 |
regmap_write(lt9611->regmap, 0x812d, 0x88); |
|
| 343 |
- else if (pclk > 70000) |
|
| 344 |
+ *postdiv = 1; |
|
| 345 |
+ } else if (pclk > 70000) {
|
|
| 346 |
regmap_write(lt9611->regmap, 0x812d, 0x99); |
|
| 347 |
- else |
|
| 348 |
+ *postdiv = 2; |
|
| 349 |
+ } else {
|
|
| 350 |
regmap_write(lt9611->regmap, 0x812d, 0xaa); |
|
| 351 |
+ *postdiv = 4; |
|
| 352 |
+ } |
|
| 353 |
|
|
| 354 |
/* |
|
| 355 |
* first divide pclk by 2 first |
|
| 356 |
@@ -351,12 +332,51 @@ static int lt9611_video_check(struct lt9611 *lt9611) |
|
| 357 |
return temp; |
|
| 358 |
} |
|
| 359 |
|
|
| 360 |
-static void lt9611_hdmi_tx_digital(struct lt9611 *lt9611) |
|
| 361 |
+static void lt9611_hdmi_set_infoframes(struct lt9611 *lt9611, |
|
| 362 |
+ struct drm_connector *connector, |
|
| 363 |
+ struct drm_display_mode *mode) |
|
| 364 |
{
|
|
| 365 |
- regmap_write(lt9611->regmap, 0x8443, 0x46 - lt9611->vic); |
|
| 366 |
- regmap_write(lt9611->regmap, 0x8447, lt9611->vic); |
|
| 367 |
- regmap_write(lt9611->regmap, 0x843d, 0x0a); /* UD1 infoframe */ |
|
| 368 |
+ union hdmi_infoframe infoframe; |
|
| 369 |
+ ssize_t len; |
|
| 370 |
+ u8 iframes = 0x0a; /* UD1 infoframe */ |
|
| 371 |
+ u8 buf[32]; |
|
| 372 |
+ int ret; |
|
| 373 |
+ int i; |
|
| 374 |
+ |
|
| 375 |
+ ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, |
|
| 376 |
+ connector, |
|
| 377 |
+ mode); |
|
| 378 |
+ if (ret < 0) |
|
| 379 |
+ goto out; |
|
| 380 |
+ |
|
| 381 |
+ len = hdmi_infoframe_pack(&infoframe, buf, sizeof(buf)); |
|
| 382 |
+ if (len < 0) |
|
| 383 |
+ goto out; |
|
| 384 |
+ |
|
| 385 |
+ for (i = 0; i < len; i++) |
|
| 386 |
+ regmap_write(lt9611->regmap, 0x8440 + i, buf[i]); |
|
| 387 |
+ |
|
| 388 |
+ ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe.vendor.hdmi, |
|
| 389 |
+ connector, |
|
| 390 |
+ mode); |
|
| 391 |
+ if (ret < 0) |
|
| 392 |
+ goto out; |
|
| 393 |
+ |
|
| 394 |
+ len = hdmi_infoframe_pack(&infoframe, buf, sizeof(buf)); |
|
| 395 |
+ if (len < 0) |
|
| 396 |
+ goto out; |
|
| 397 |
+ |
|
| 398 |
+ for (i = 0; i < len; i++) |
|
| 399 |
+ regmap_write(lt9611->regmap, 0x8474 + i, buf[i]); |
|
| 400 |
+ |
|
| 401 |
+ iframes |= 0x20; |
|
| 402 |
+ |
|
| 403 |
+out: |
|
| 404 |
+ regmap_write(lt9611->regmap, 0x843d, iframes); /* UD1 infoframe */ |
|
| 405 |
+} |
|
| 406 |
|
|
| 407 |
+static void lt9611_hdmi_tx_digital(struct lt9611 *lt9611) |
|
| 408 |
+{
|
|
| 409 |
regmap_write(lt9611->regmap, 0x82d6, 0x8c); |
|
| 410 |
regmap_write(lt9611->regmap, 0x82d7, 0x04); |
|
| 411 |
} |
|
| 412 |
@@ -446,12 +466,11 @@ static void lt9611_sleep_setup(struct lt9611 *lt9611) |
|
| 413 |
{ 0x8023, 0x01 },
|
|
| 414 |
{ 0x8157, 0x03 }, /* set addr pin as output */
|
|
| 415 |
{ 0x8149, 0x0b },
|
|
| 416 |
- { 0x8151, 0x30 }, /* disable IRQ */
|
|
| 417 |
+ |
|
| 418 |
{ 0x8102, 0x48 }, /* MIPI Rx power down */
|
|
| 419 |
{ 0x8123, 0x80 },
|
|
| 420 |
{ 0x8130, 0x00 },
|
|
| 421 |
- { 0x8100, 0x01 }, /* bandgap power down */
|
|
| 422 |
- { 0x8101, 0x00 }, /* system clk power down */
|
|
| 423 |
+ { 0x8011, 0x0a },
|
|
| 424 |
}; |
|
| 425 |
|
|
| 426 |
regmap_multi_reg_write(lt9611->regmap, |
|
| 427 |
@@ -517,7 +536,7 @@ static void lt9611_reset(struct lt9611 *lt9611) |
|
| 428 |
msleep(20); |
|
| 429 |
|
|
| 430 |
gpiod_set_value_cansleep(lt9611->reset_gpio, 1); |
|
| 431 |
- msleep(100); |
|
| 432 |
+ msleep(20); |
|
| 433 |
} |
|
| 434 |
|
|
| 435 |
static void lt9611_assert_5v(struct lt9611 *lt9611) |
|
| 436 |
@@ -562,31 +581,14 @@ static int lt9611_regulator_enable(struct lt9611 *lt9611) |
|
| 437 |
return 0; |
|
| 438 |
} |
|
| 439 |
|
|
| 440 |
-static struct lt9611_mode *lt9611_find_mode(const struct drm_display_mode *mode) |
|
| 441 |
-{
|
|
| 442 |
- int i; |
|
| 443 |
- |
|
| 444 |
- for (i = 0; i < ARRAY_SIZE(lt9611_modes); i++) {
|
|
| 445 |
- if (lt9611_modes[i].hdisplay == mode->hdisplay && |
|
| 446 |
- lt9611_modes[i].vdisplay == mode->vdisplay && |
|
| 447 |
- lt9611_modes[i].vrefresh == drm_mode_vrefresh(mode)) {
|
|
| 448 |
- return <9611_modes[i]; |
|
| 449 |
- } |
|
| 450 |
- } |
|
| 451 |
- |
|
| 452 |
- return NULL; |
|
| 453 |
-} |
|
| 454 |
- |
|
| 455 |
-/* connector funcs */ |
|
| 456 |
-static enum drm_connector_status |
|
| 457 |
-lt9611_connector_detect(struct drm_connector *connector, bool force) |
|
| 458 |
+static enum drm_connector_status lt9611_bridge_detect(struct drm_bridge *bridge) |
|
| 459 |
{
|
|
| 460 |
- struct lt9611 *lt9611 = connector_to_lt9611(connector); |
|
| 461 |
+ struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 462 |
unsigned int reg_val = 0; |
|
| 463 |
int connected = 0; |
|
| 464 |
|
|
| 465 |
regmap_read(lt9611->regmap, 0x825e, ®_val); |
|
| 466 |
- connected = (reg_val & BIT(2)); |
|
| 467 |
+ connected = (reg_val & (BIT(2) | BIT(0))); |
|
| 468 |
|
|
| 469 |
lt9611->status = connected ? connector_status_connected : |
|
| 470 |
connector_status_disconnected; |
|
| 471 |
@@ -675,34 +677,37 @@ lt9611_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) |
|
| 472 |
return 0; |
|
| 473 |
} |
|
| 474 |
|
|
| 475 |
-static int lt9611_connector_get_modes(struct drm_connector *connector) |
|
| 476 |
+/* bridge funcs */ |
|
| 477 |
+static void |
|
| 478 |
+lt9611_bridge_atomic_enable(struct drm_bridge *bridge, |
|
| 479 |
+ struct drm_bridge_state *old_bridge_state) |
|
| 480 |
{
|
|
| 481 |
- struct lt9611 *lt9611 = connector_to_lt9611(connector); |
|
| 482 |
- unsigned int count; |
|
| 483 |
- struct edid *edid; |
|
| 484 |
- |
|
| 485 |
- lt9611_power_on(lt9611); |
|
| 486 |
- edid = drm_do_get_edid(connector, lt9611_get_edid_block, lt9611); |
|
| 487 |
- drm_connector_update_edid_property(connector, edid); |
|
| 488 |
- count = drm_add_edid_modes(connector, edid); |
|
| 489 |
- kfree(edid); |
|
| 490 |
+ struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 491 |
+ struct drm_atomic_state *state = old_bridge_state->base.state; |
|
| 492 |
+ struct drm_connector *connector; |
|
| 493 |
+ struct drm_connector_state *conn_state; |
|
| 494 |
+ struct drm_crtc_state *crtc_state; |
|
| 495 |
+ struct drm_display_mode *mode; |
|
| 496 |
+ unsigned int postdiv; |
|
| 497 |
+ |
|
| 498 |
+ connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); |
|
| 499 |
+ if (WARN_ON(!connector)) |
|
| 500 |
+ return; |
|
| 501 |
|
|
| 502 |
- return count; |
|
| 503 |
-} |
|
| 504 |
+ conn_state = drm_atomic_get_new_connector_state(state, connector); |
|
| 505 |
+ if (WARN_ON(!conn_state)) |
|
| 506 |
+ return; |
|
| 507 |
|
|
| 508 |
-static enum drm_mode_status |
|
| 509 |
-lt9611_connector_mode_valid(struct drm_connector *connector, |
|
| 510 |
- struct drm_display_mode *mode) |
|
| 511 |
-{
|
|
| 512 |
- struct lt9611_mode *lt9611_mode = lt9611_find_mode(mode); |
|
| 513 |
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); |
|
| 514 |
+ if (WARN_ON(!crtc_state)) |
|
| 515 |
+ return; |
|
| 516 |
|
|
| 517 |
- return lt9611_mode ? MODE_OK : MODE_BAD; |
|
| 518 |
-} |
|
| 519 |
+ mode = &crtc_state->adjusted_mode; |
|
| 520 |
|
|
| 521 |
-/* bridge funcs */ |
|
| 522 |
-static void lt9611_bridge_enable(struct drm_bridge *bridge) |
|
| 523 |
-{
|
|
| 524 |
- struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 525 |
+ lt9611_mipi_input_digital(lt9611, mode); |
|
| 526 |
+ lt9611_pll_setup(lt9611, mode, &postdiv); |
|
| 527 |
+ lt9611_mipi_video_setup(lt9611, mode); |
|
| 528 |
+ lt9611_pcr_setup(lt9611, mode, postdiv); |
|
| 529 |
|
|
| 530 |
if (lt9611_power_on(lt9611)) {
|
|
| 531 |
dev_err(lt9611->dev, "power on failed\n"); |
|
| 532 |
@@ -710,10 +715,11 @@ static void lt9611_bridge_enable(struct drm_bridge *bridge) |
|
| 533 |
} |
|
| 534 |
|
|
| 535 |
lt9611_mipi_input_analog(lt9611); |
|
| 536 |
+ lt9611_hdmi_set_infoframes(lt9611, connector, mode); |
|
| 537 |
lt9611_hdmi_tx_digital(lt9611); |
|
| 538 |
lt9611_hdmi_tx_phy(lt9611); |
|
| 539 |
|
|
| 540 |
- msleep(500); |
|
| 541 |
+ //msleep(500); |
|
| 542 |
|
|
| 543 |
lt9611_video_check(lt9611); |
|
| 544 |
|
|
| 545 |
@@ -721,7 +727,9 @@ static void lt9611_bridge_enable(struct drm_bridge *bridge) |
|
| 546 |
regmap_write(lt9611->regmap, 0x8130, 0xea); |
|
| 547 |
} |
|
| 548 |
|
|
| 549 |
-static void lt9611_bridge_disable(struct drm_bridge *bridge) |
|
| 550 |
+static void |
|
| 551 |
+lt9611_bridge_atomic_disable(struct drm_bridge *bridge, |
|
| 552 |
+ struct drm_bridge_state *old_bridge_state) |
|
| 553 |
{
|
|
| 554 |
struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 555 |
int ret; |
|
| 556 |
@@ -739,25 +747,10 @@ static void lt9611_bridge_disable(struct drm_bridge *bridge) |
|
| 557 |
} |
|
| 558 |
} |
|
| 559 |
|
|
| 560 |
-static struct |
|
| 561 |
-drm_connector_helper_funcs lt9611_bridge_connector_helper_funcs = {
|
|
| 562 |
- .get_modes = lt9611_connector_get_modes, |
|
| 563 |
- .mode_valid = lt9611_connector_mode_valid, |
|
| 564 |
-}; |
|
| 565 |
- |
|
| 566 |
-static const struct drm_connector_funcs lt9611_bridge_connector_funcs = {
|
|
| 567 |
- .fill_modes = drm_helper_probe_single_connector_modes, |
|
| 568 |
- .detect = lt9611_connector_detect, |
|
| 569 |
- .destroy = drm_connector_cleanup, |
|
| 570 |
- .reset = drm_atomic_helper_connector_reset, |
|
| 571 |
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
|
| 572 |
- .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
|
| 573 |
-}; |
|
| 574 |
- |
|
| 575 |
static struct mipi_dsi_device *lt9611_attach_dsi(struct lt9611 *lt9611, |
|
| 576 |
struct device_node *dsi_node) |
|
| 577 |
{
|
|
| 578 |
- const struct mipi_dsi_device_info info = { "lt9611", 0, NULL };
|
|
| 579 |
+ const struct mipi_dsi_device_info info = { "lt9611", 0, lt9611->dev->of_node};
|
|
| 580 |
struct mipi_dsi_device *dsi; |
|
| 581 |
struct mipi_dsi_host *host; |
|
| 582 |
int ret; |
|
| 583 |
@@ -802,42 +795,12 @@ static void lt9611_bridge_detach(struct drm_bridge *bridge) |
|
| 584 |
mipi_dsi_device_unregister(lt9611->dsi0); |
|
| 585 |
} |
|
| 586 |
|
|
| 587 |
-static int lt9611_connector_init(struct drm_bridge *bridge, struct lt9611 *lt9611) |
|
| 588 |
-{
|
|
| 589 |
- int ret; |
|
| 590 |
- |
|
| 591 |
- ret = drm_connector_init(bridge->dev, <9611->connector, |
|
| 592 |
- <9611_bridge_connector_funcs, |
|
| 593 |
- DRM_MODE_CONNECTOR_HDMIA); |
|
| 594 |
- if (ret) {
|
|
| 595 |
- DRM_ERROR("Failed to initialize connector with drm\n");
|
|
| 596 |
- return ret; |
|
| 597 |
- } |
|
| 598 |
- |
|
| 599 |
- drm_connector_helper_add(<9611->connector, |
|
| 600 |
- <9611_bridge_connector_helper_funcs); |
|
| 601 |
- drm_connector_attach_encoder(<9611->connector, bridge->encoder); |
|
| 602 |
- |
|
| 603 |
- if (!bridge->encoder) {
|
|
| 604 |
- DRM_ERROR("Parent encoder object not found");
|
|
| 605 |
- return -ENODEV; |
|
| 606 |
- } |
|
| 607 |
- |
|
| 608 |
- return 0; |
|
| 609 |
-} |
|
| 610 |
- |
|
| 611 |
static int lt9611_bridge_attach(struct drm_bridge *bridge, |
|
| 612 |
enum drm_bridge_attach_flags flags) |
|
| 613 |
{
|
|
| 614 |
struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 615 |
int ret; |
|
| 616 |
|
|
| 617 |
- if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
|
|
| 618 |
- ret = lt9611_connector_init(bridge, lt9611); |
|
| 619 |
- if (ret < 0) |
|
| 620 |
- return ret; |
|
| 621 |
- } |
|
| 622 |
- |
|
| 623 |
/* Attach primary DSI */ |
|
| 624 |
lt9611->dsi0 = lt9611_attach_dsi(lt9611, lt9611->dsi0_node); |
|
| 625 |
if (IS_ERR(lt9611->dsi0)) |
|
| 626 |
@@ -852,11 +815,11 @@ static int lt9611_bridge_attach(struct drm_bridge *bridge, |
|
| 627 |
} |
|
| 628 |
} |
|
| 629 |
|
|
| 630 |
- return 0; |
|
| 631 |
+ return drm_bridge_attach(bridge->encoder, lt9611->next_bridge, |
|
| 632 |
+ bridge, flags); |
|
| 633 |
|
|
| 634 |
err_unregister_dsi0: |
|
| 635 |
lt9611_bridge_detach(bridge); |
|
| 636 |
- drm_connector_cleanup(<9611->connector); |
|
| 637 |
mipi_dsi_device_unregister(lt9611->dsi0); |
|
| 638 |
|
|
| 639 |
return ret; |
|
| 640 |
@@ -866,74 +829,54 @@ static enum drm_mode_status lt9611_bridge_mode_valid(struct drm_bridge *bridge, |
|
| 641 |
const struct drm_display_info *info, |
|
| 642 |
const struct drm_display_mode *mode) |
|
| 643 |
{
|
|
| 644 |
- struct lt9611_mode *lt9611_mode = lt9611_find_mode(mode); |
|
| 645 |
struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 646 |
|
|
| 647 |
- if (!lt9611_mode) |
|
| 648 |
- return MODE_BAD; |
|
| 649 |
- else if (lt9611_mode->intfs > 1 && !lt9611->dsi1) |
|
| 650 |
+ if (mode->hdisplay > 3840) |
|
| 651 |
+ return MODE_BAD_HVALUE; |
|
| 652 |
+ |
|
| 653 |
+ if (mode->vdisplay > 2160) |
|
| 654 |
+ return MODE_BAD_VVALUE; |
|
| 655 |
+ |
|
| 656 |
+ if (mode->hdisplay == 3840 && |
|
| 657 |
+ mode->vdisplay == 2160 && |
|
| 658 |
+ drm_mode_vrefresh(mode) > 30) |
|
| 659 |
+ return MODE_CLOCK_HIGH; |
|
| 660 |
+ |
|
| 661 |
+ if (mode->hdisplay > 2000 && !lt9611->dsi1_node) |
|
| 662 |
return MODE_PANEL; |
|
| 663 |
else |
|
| 664 |
return MODE_OK; |
|
| 665 |
} |
|
| 666 |
|
|
| 667 |
-static void lt9611_bridge_pre_enable(struct drm_bridge *bridge) |
|
| 668 |
+static void lt9611_bridge_atomic_pre_enable(struct drm_bridge *bridge, |
|
| 669 |
+ struct drm_bridge_state *old_bridge_state) |
|
| 670 |
{
|
|
| 671 |
struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 672 |
+ static const struct reg_sequence reg_cfg[] = {
|
|
| 673 |
+ { 0x8102, 0x12 },
|
|
| 674 |
+ { 0x8123, 0x40 },
|
|
| 675 |
+ { 0x8130, 0xea },
|
|
| 676 |
+ { 0x8011, 0xfa },
|
|
| 677 |
+ }; |
|
| 678 |
|
|
| 679 |
if (!lt9611->sleep) |
|
| 680 |
return; |
|
| 681 |
|
|
| 682 |
- lt9611_reset(lt9611); |
|
| 683 |
- regmap_write(lt9611->regmap, 0x80ee, 0x01); |
|
| 684 |
+ regmap_multi_reg_write(lt9611->regmap, |
|
| 685 |
+ reg_cfg, ARRAY_SIZE(reg_cfg)); |
|
| 686 |
|
|
| 687 |
lt9611->sleep = false; |
|
| 688 |
} |
|
| 689 |
|
|
| 690 |
-static void lt9611_bridge_post_disable(struct drm_bridge *bridge) |
|
| 691 |
+static void |
|
| 692 |
+lt9611_bridge_atomic_post_disable(struct drm_bridge *bridge, |
|
| 693 |
+ struct drm_bridge_state *old_bridge_state) |
|
| 694 |
{
|
|
| 695 |
struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 696 |
|
|
| 697 |
lt9611_sleep_setup(lt9611); |
|
| 698 |
} |
|
| 699 |
|
|
| 700 |
-static void lt9611_bridge_mode_set(struct drm_bridge *bridge, |
|
| 701 |
- const struct drm_display_mode *mode, |
|
| 702 |
- const struct drm_display_mode *adj_mode) |
|
| 703 |
-{
|
|
| 704 |
- struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 705 |
- struct hdmi_avi_infoframe avi_frame; |
|
| 706 |
- int ret; |
|
| 707 |
- |
|
| 708 |
- lt9611_bridge_pre_enable(bridge); |
|
| 709 |
- |
|
| 710 |
- lt9611_mipi_input_digital(lt9611, mode); |
|
| 711 |
- lt9611_pll_setup(lt9611, mode); |
|
| 712 |
- lt9611_mipi_video_setup(lt9611, mode); |
|
| 713 |
- lt9611_pcr_setup(lt9611, mode); |
|
| 714 |
- |
|
| 715 |
- ret = drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, |
|
| 716 |
- <9611->connector, |
|
| 717 |
- mode); |
|
| 718 |
- if (!ret) |
|
| 719 |
- lt9611->vic = avi_frame.video_code; |
|
| 720 |
-} |
|
| 721 |
- |
|
| 722 |
-static enum drm_connector_status lt9611_bridge_detect(struct drm_bridge *bridge) |
|
| 723 |
-{
|
|
| 724 |
- struct lt9611 *lt9611 = bridge_to_lt9611(bridge); |
|
| 725 |
- unsigned int reg_val = 0; |
|
| 726 |
- int connected; |
|
| 727 |
- |
|
| 728 |
- regmap_read(lt9611->regmap, 0x825e, ®_val); |
|
| 729 |
- connected = reg_val & BIT(2); |
|
| 730 |
- |
|
| 731 |
- lt9611->status = connected ? connector_status_connected : |
|
| 732 |
- connector_status_disconnected; |
|
| 733 |
- |
|
| 734 |
- return lt9611->status; |
|
| 735 |
-} |
|
| 736 |
- |
|
| 737 |
static struct edid *lt9611_bridge_get_edid(struct drm_bridge *bridge, |
|
| 738 |
struct drm_connector *connector) |
|
| 739 |
{
|
|
| 740 |
@@ -954,13 +897,17 @@ static const struct drm_bridge_funcs lt9611_bridge_funcs = {
|
|
| 741 |
.attach = lt9611_bridge_attach, |
|
| 742 |
.detach = lt9611_bridge_detach, |
|
| 743 |
.mode_valid = lt9611_bridge_mode_valid, |
|
| 744 |
- .enable = lt9611_bridge_enable, |
|
| 745 |
- .disable = lt9611_bridge_disable, |
|
| 746 |
- .post_disable = lt9611_bridge_post_disable, |
|
| 747 |
- .mode_set = lt9611_bridge_mode_set, |
|
| 748 |
.detect = lt9611_bridge_detect, |
|
| 749 |
.get_edid = lt9611_bridge_get_edid, |
|
| 750 |
.hpd_enable = lt9611_bridge_hpd_enable, |
|
| 751 |
+ |
|
| 752 |
+ .atomic_pre_enable = lt9611_bridge_atomic_pre_enable, |
|
| 753 |
+ .atomic_enable = lt9611_bridge_atomic_enable, |
|
| 754 |
+ .atomic_disable = lt9611_bridge_atomic_disable, |
|
| 755 |
+ .atomic_post_disable = lt9611_bridge_atomic_post_disable, |
|
| 756 |
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, |
|
| 757 |
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, |
|
| 758 |
+ .atomic_reset = drm_atomic_helper_bridge_reset, |
|
| 759 |
}; |
|
| 760 |
|
|
| 761 |
static int lt9611_parse_dt(struct device *dev, |
|
| 762 |
@@ -976,7 +923,7 @@ static int lt9611_parse_dt(struct device *dev, |
|
| 763 |
|
|
| 764 |
lt9611->ac_mode = of_property_read_bool(dev->of_node, "lt,ac-mode"); |
|
| 765 |
|
|
| 766 |
- return 0; |
|
| 767 |
+ return drm_of_find_panel_or_bridge(dev->of_node, 2, -1, NULL, <9611->next_bridge); |
|
| 768 |
} |
|
| 769 |
|
|
| 770 |
static int lt9611_gpio_init(struct lt9611 *lt9611) |
|
| 771 |
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c |
|
| 772 |
index 8bb2f8b5f5c7..5e4356478ddc 100644 |
|
| 773 |
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c |
|
| 774 |
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c |
|
| 775 |
@@ -793,58 +793,6 @@ void mtk_dsi_ddp_stop(struct device *dev) |
|
| 776 |
mtk_dsi_poweroff(dsi); |
|
| 777 |
} |
|
| 778 |
|
|
| 779 |
-static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi) |
|
| 780 |
-{
|
|
| 781 |
- int ret; |
|
| 782 |
- int indicated_disp_path = -1; |
|
| 783 |
- |
|
| 784 |
- ret = drm_simple_encoder_init(drm, &dsi->encoder, |
|
| 785 |
- DRM_MODE_ENCODER_DSI); |
|
| 786 |
- if (ret) {
|
|
| 787 |
- DRM_ERROR("Failed to encoder init to drm\n");
|
|
| 788 |
- return ret; |
|
| 789 |
- } |
|
| 790 |
- |
|
| 791 |
- if (of_find_property(dsi->host.dev->of_node, "mediatek,indicated-display-path", &ret)) {
|
|
| 792 |
- ret = of_property_read_u32(dsi->host.dev->of_node, |
|
| 793 |
- "mediatek,indicated-display-path", |
|
| 794 |
- &indicated_disp_path); |
|
| 795 |
- if (ret) {
|
|
| 796 |
- dev_err(dsi->host.dev, "Failed to get indicated-display-path id\n"); |
|
| 797 |
- return ret; |
|
| 798 |
- } |
|
| 799 |
- if (indicated_disp_path < 0 || indicated_disp_path >= MAX_CRTC) {
|
|
| 800 |
- dev_err(dsi->host.dev, "Wrong indicated-display-path id read from dts !\n"); |
|
| 801 |
- indicated_disp_path = -1; |
|
| 802 |
- } |
|
| 803 |
- } |
|
| 804 |
- |
|
| 805 |
- if (indicated_disp_path == -1) |
|
| 806 |
- dsi->encoder.possible_crtcs = |
|
| 807 |
- mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev); |
|
| 808 |
- else |
|
| 809 |
- dsi->encoder.possible_crtcs = (1 << indicated_disp_path); |
|
| 810 |
- |
|
| 811 |
- ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL, |
|
| 812 |
- DRM_BRIDGE_ATTACH_NO_CONNECTOR); |
|
- « Previous
- 1
- …
- 5
- 6
- 7
- Next »