SB35 issue tracking

    cp -a ${DEPLOY_DIR_IMAGE}/devicetree ${tmp_pack_dir}

UBOOT_MACHINE = "mt8365_sb35_defconfig"

MACHINE_FEATURES:append = " alsa usbgadget usbhost wifi screen"

pcm.speaker {

       type plug

       slave {

               pcm "hw:mtsndcard,1,0"

               channels 2

       }

}

		value true

		value true

SRCREV_tfa = "31d4d84a48551686f5ae1916c8fb6416ca16a83b"

From 05bb8f47e4d376d05f30ef95b170ac51aaac6478 Mon Sep 17 00:00:00 2001

From: Rockefeller Lin <rockefeller.lin@innocomm.com>

Date: Wed, 24 May 2023 12:18:47 +0800

Subject: [PATCH 1/1] Add dedicated sb35 defconfig and dts files

The defconfig and dts files are copied from mt8365-pumpkin.

---

 arch/arm/dts/Makefile         |   1 +

 arch/arm/dts/mt8365-sb35.dts  | 164 ++++++++++++++++++++++++++++++++++

 configs/mt8365_sb35_defconfig |  97 ++++++++++++++++++++

 3 files changed, 262 insertions(+)

 create mode 100644 arch/arm/dts/mt8365-sb35.dts

 create mode 100644 configs/mt8365_sb35_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile

index 7b216bf62a..ac852fab60 100644

--- a/arch/arm/dts/Makefile

+++ b/arch/arm/dts/Makefile

@@ -1237,6 +1237,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \

 	mt8195-demo.dtb \

 	mt8195-evb-ufs.dtb \

 	mt8365-pumpkin.dtb \

+	mt8365-sb35.dtb \

 	mt8512-bm1-emmc.dtb \

 	mt8516-pumpkin.dtb \

 	mt8518-ap1-emmc.dtb \

diff --git a/arch/arm/dts/mt8365-sb35.dts b/arch/arm/dts/mt8365-sb35.dts

new file mode 100644

index 0000000000..5f57657026

--- /dev/null

+++ b/arch/arm/dts/mt8365-sb35.dts

@@ -0,0 +1,164 @@

+// SPDX-License-Identifier: GPL-2.0 OR MIT

+/*

+ * Copyright (C) 2021 BayLibre SAS.

+ * Author: Fabien Parent <fparent@baylibre.com>

+ */

+

+/dts-v1/;

+

+#include <config.h>

+#include "mt8365.dtsi"

+#include "mt6357.dtsi"

+

+/ {

+	model = "MT8365 SB35 board";

+	compatible = "mediatek,mt8365-sb35", "mediatek,mt8365";

+

+	memory@40000000 {

+		device_type = "memory";

+		reg = <0 0x40000000 0 0x40000000>;

+	};

+

+	firmware: firmware {

+		optee {

+			compatible = "linaro,optee-tz";

+			method = "smc";

+		};

+	};

+

+	reserved-memory {

+		#address-cells = <2>;

+		#size-cells = <2>;

+		ranges;

+

+		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */

+		bl31_secmon_reserved: secmon@43000000 {

+			no-map;

+			reg = <0 0x43000000 0 0x30000>;

+		};

+

+		/* 12 MiB reserved for OP-TEE (BL32)

+		 * +-----------------------+ 0x43e0_0000

+		 * |      SHMEM 2MiB       |

+		 * +-----------------------+ 0x43c0_0000

+		 * |        | TA_RAM  8MiB |

+		 * + TZDRAM +--------------+ 0x4340_0000

+		 * |        | TEE_RAM 2MiB |

+		 * +-----------------------+ 0x4320_0000

+		 */

+		optee_reserved: optee@43200000 {

+			no-map;

+			reg = <0 0x43200000 0 0x00c00000>;

+		};

+	};

+

+	chosen {

+		stdout-path = &uart0;

+	};

+};

+

+&uart0 {

+	status = "okay";

+};

+

+&mmc0 {

+	bus-width = <4>;

+	max-frequency = <200000000>;

+	cap-mmc-highspeed;

+	mmc-hs200-1_8v;

+	cap-mmc-hw-reset;

+	vmmc-supply = <&mt6357_vemc_reg>;

+	vqmmc-supply = <&mt6357_vio18_reg>;

+	non-removable;

+	status = "okay";

+};

+

+&usb {

+	status = "okay";

+};

+

+&ssusb {

+	mediatek,force-vbus;

+	maximum-speed = "high-speed";

+	dr_mode = "peripheral";

+	status = "okay";

+};

+

+&dpi0 {

+	dpi_dual_edge;

+	pinctrl-names = "default", "sleep";

+	pinctrl-0 = <&dpi_pin_func>;

+	pinctrl-1 = <&dpi_pin_gpio>;

+	status = "okay";

+};

+

+&i2c0 {

+	pinctrl-names = "default";

+	pinctrl-0 = <&i2c0_pins_default>;

+	clock-frequency = <100000>;

+	status = "okay";

+};

+

+&i2c1 {

+	pinctrl-names = "default";

+	pinctrl-0 = <&i2c1_pins_default>;

+	clock-frequency = <100000>;

+	status = "okay";

+

+	it66121hdmitx {

+		compatible = "ite,it66121";

+		reg = <0x4c>;

+		pinctrl-names = "default";

+		pinctrl-0 = <&ite_pins_default>;

+		vcn33-supply = <&mt6357_vcn33_bt_reg>;

+		vcn18-supply = <&mt6357_vcn18_reg>;

+		vrf12-supply = <&mt6357_vrf12_reg>;

+		reset-gpios = <&gpio 69 GPIO_ACTIVE_LOW>;

+	};

+};

+

+&i2c2 {

+	pinctrl-names = "default";

+	pinctrl-0 = <&i2c2_pins_default>;

+	clock-frequency = <100000>;

+	status = "okay";

+};

+

+&pio {

+	dpi_pin_func: dpi_pin_func {

+		function = "dpi";

+		groups =  "dpi_enable";

+	};

+

+	dpi_pin_gpio: dpi_pin_gpio {

+		function = "dpi";

+		groups =  "dpi_sleep";

+	};

+

+	i2c0_pins_default: i2c0_pins_default {

+		function = "i2c";

+		groups = "i2c0";

+	};

+

+	i2c1_pins_default: i2c1_pins_default {

+		function = "i2c";

+		groups = "i2c1";

+	};

+

+	i2c2_pins_default: i2c2_pins_default {

+		function = "i2c";

+		groups = "i2c2";

+	};

+

+	ite_pins_default: ite_pins_default {

+		pins_rst_ite {

+			pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;

+			output-high;

+		};

+

+		pins_irq_ite {

+			pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;

+			input-enable;

+		};

+	};

+};

diff --git a/configs/mt8365_sb35_defconfig b/configs/mt8365_sb35_defconfig

new file mode 100644

index 0000000000..3c25705aab

--- /dev/null

+++ b/configs/mt8365_sb35_defconfig

@@ -0,0 +1,97 @@

+CONFIG_ARM=y

+CONFIG_COUNTER_FREQUENCY=13000000

+CONFIG_POSITION_INDEPENDENT=y

+CONFIG_ARCH_MEDIATEK=y

+CONFIG_SYS_TEXT_BASE=0x4c000000

+CONFIG_SYS_MALLOC_F_LEN=0x4000

+CONFIG_NR_DRAM_BANKS=1

+CONFIG_ENV_SIZE=0x1000

+CONFIG_ENV_OFFSET=0x0

+CONFIG_DM_GPIO=y

+CONFIG_DEFAULT_DEVICE_TREE="mt8365-sb35"

+CONFIG_TARGET_MT8365=y

+CONFIG_DEBUG_UART_BASE=0x11002000

+CONFIG_DEBUG_UART_CLOCK=26000000

+CONFIG_SYS_LOAD_ADDR=0x4c000000

+CONFIG_DEBUG_UART=y

+CONFIG_ENV_VARS_UBOOT_CONFIG=y

+# CONFIG_ANDROID_BOOT_IMAGE is not set

+CONFIG_FIT=y

+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set

+CONFIG_USE_BOOTCOMMAND=y

+CONFIG_BOOTCOMMAND="run distro_bootcmd"

+CONFIG_DEFAULT_FDT_FILE="mt8365-sb35"

+# CONFIG_DISPLAY_BOARDINFO is not set

+CONFIG_HUSH_PARSER=y

+# CONFIG_CMD_CONSOLE is not set

+# CONFIG_CMD_BOOTD is not set

+# CONFIG_CMD_ELF is not set

+# CONFIG_CMD_GO is not set

+# CONFIG_CMD_IMI is not set

+# CONFIG_CMD_XIMG is not set

+# CONFIG_CMD_CRC32 is not set

+CONFIG_CMD_CLK=y

+CONFIG_CMD_DFU=y

+CONFIG_CMD_DM=y

+CONFIG_CMD_GPT=y

+# CONFIG_RANDOM_UUID is not set

+CONFIG_CMD_I2C=y

+# CONFIG_CMD_LOADB is not set

+# CONFIG_CMD_LOADS is not set

+CONFIG_CMD_MMC=y

+CONFIG_CMD_PART=y

+CONFIG_CMD_USB=y

+CONFIG_CMD_USB_MASS_STORAGE=y

+# CONFIG_CMD_ITEST is not set

+CONFIG_CMD_DHCP=y

+# CONFIG_CMD_BLOCK_CACHE is not set

+CONFIG_CMD_SYSBOOT=y

+CONFIG_CMD_EXT4=y

+CONFIG_CMD_FAT=y

+CONFIG_CMD_FS_GENERIC=y

+CONFIG_ISO_PARTITION=y

+CONFIG_ENV_IS_IN_MMC=y

+CONFIG_SYS_MMC_ENV_PART=2

+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

+CONFIG_ENV_IMPORT_FDT=y

+CONFIG_DEVRES=y

+CONFIG_CLK=y

+CONFIG_DFU_MMC=y

+CONFIG_USB_FUNCTION_FASTBOOT=y

+CONFIG_FASTBOOT_BUF_ADDR=0x4d000000

+CONFIG_FASTBOOT_BUF_SIZE=0x8000000

+CONFIG_FASTBOOT_FLASH=y

+CONFIG_FASTBOOT_FLASH_MMC_DEV=0

+CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y

+CONFIG_DM_I2C=y

+CONFIG_SYS_I2C_MTK=y

+# CONFIG_INPUT is not set

+# CONFIG_MMC_QUIRKS is not set

+CONFIG_MMC_MTK=y

+CONFIG_PHY=y

+CONFIG_PHY_MTK_TPHY=y

+CONFIG_PINCTRL=y

+CONFIG_PINCONF=y

+CONFIG_PINCTRL_MT8365=y

+CONFIG_DM_RTC=y

+CONFIG_RTC_EMULATION=y

+CONFIG_BAUDRATE=921600

+CONFIG_DM_SERIAL=y

+CONFIG_DEBUG_UART_ANNOUNCE=y

+CONFIG_MTK_SERIAL=y

+CONFIG_USB=y

+CONFIG_DM_USB_GADGET=y

+CONFIG_USB_XHCI_HCD=y

+CONFIG_USB_XHCI_MTK=y

+CONFIG_USB_MTU3=y

+CONFIG_USB_STORAGE=y

+CONFIG_USB_KEYBOARD=y

+CONFIG_USB_HOST_ETHER=y

+CONFIG_USB_GADGET=y

+CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d

+CONFIG_USB_GADGET_PRODUCT_NUM=0x201c

+CONFIG_USB_ETHER=y

+CONFIG_WDT=y

+CONFIG_WDT_MTK=y

+CONFIG_OF_LIBFDT_OVERLAY=y

+CONFIG_LMB_MAX_REGIONS=16

-- 

2.25.1

From 6061bcfb8f1dfc47714beae179be4bc4e4223062 Mon Sep 17 00:00:00 2001

From: Rockefeller Lin <rockefeller.lin@innocomm.com>

Date: Fri, 7 Apr 2023 03:29:44 +0000

Subject: [PATCH] Set bootdelay to 0 to save ~3secs of booting time

Set bootdelay to 0 to save ~3secs of booting time

---

 configs/mt8365_sb35_defconfig        | 1 +

 1 files changed, 1 insertions(+)

diff --git a/configs/mt8365_sb35_defconfig b/configs/mt8365_sb35_defconfig

index 204b97244b..ccf8c26892 100644

--- a/configs/mt8365_sb35_defconfig

+++ b/configs/mt8365_sb35_defconfig

@@ -96,3 +96,4 @@ CONFIG_WDT=y

 CONFIG_WDT_MTK=y

 CONFIG_OF_LIBFDT_OVERLAY=y

 CONFIG_LMB_MAX_REGIONS=16

+CONFIG_BOOTDELAY=0

-- 

2.25.1

From 29ec664a6ac95151a2967527c1a9d04603aa62c3 Mon Sep 17 00:00:00 2001

From: Rockefeller Lin <rockefeller.lin@innocomm.com>

Date: Wed, 24 May 2023 12:57:31 +0800

Subject: [PATCH 1/1] Remove DPI and it66121 from sb35 dts

The HDMI bridge on SB35 EVK is lt9611 and interface is DSI, so remove

DPI and it66121 nodes.

The lt9611 node is added but disable it because MTK DSI is still not supported yet.

---

 arch/arm/dts/mt8365-sb35.dts | 66 +++++++++++++++++++-----------------

 1 file changed, 35 insertions(+), 31 deletions(-)

diff --git a/arch/arm/dts/mt8365-sb35.dts b/arch/arm/dts/mt8365-sb35.dts

index 5f57657026..b645d276a6 100644

--- a/arch/arm/dts/mt8365-sb35.dts

+++ b/arch/arm/dts/mt8365-sb35.dts

@@ -84,14 +84,6 @@

 	status = "okay";

 };

-&dpi0 {

-	dpi_dual_edge;

-	pinctrl-names = "default", "sleep";

-	pinctrl-0 = <&dpi_pin_func>;

-	pinctrl-1 = <&dpi_pin_gpio>;

-	status = "okay";

-};

-

 &i2c0 {

 	pinctrl-names = "default";

 	pinctrl-0 = <&i2c0_pins_default>;

@@ -105,16 +97,15 @@

 	clock-frequency = <100000>;

 	status = "okay";

-	it66121hdmitx {

-		compatible = "ite,it66121";

+#if 0

+	lt9611hdmitx {

+		compatible = "lontium,lt9611";

 		reg = <0x4c>;

 		pinctrl-names = "default";

-		pinctrl-0 = <&ite_pins_default>;

-		vcn33-supply = <&mt6357_vcn33_bt_reg>;

-		vcn18-supply = <&mt6357_vcn18_reg>;

-		vrf12-supply = <&mt6357_vrf12_reg>;

-		reset-gpios = <&gpio 69 GPIO_ACTIVE_LOW>;

+		pinctrl-0 = <&hdmi_pins_default>;

+		reset-gpios = <&gpio 20 GPIO_ACTIVE_LOW>;

 	};

+#endif

 };

 &i2c2 {

@@ -125,16 +116,6 @@

 };

 &pio {

-	dpi_pin_func: dpi_pin_func {

-		function = "dpi";

-		groups =  "dpi_enable";

-	};

-

-	dpi_pin_gpio: dpi_pin_gpio {

-		function = "dpi";

-		groups =  "dpi_sleep";

-	};

-

 	i2c0_pins_default: i2c0_pins_default {

 		function = "i2c";

 		groups = "i2c0";

@@ -150,15 +131,38 @@

 		groups = "i2c2";

 	};

-	ite_pins_default: ite_pins_default {

-		pins_rst_ite {

-			pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;

-			output-high;

+#if 0

+	hdmi_pins_default: hdmi_pins_default {

+		pin_pwr_en {

+			pinmux = <MT8365_PIN_4_GPIO4__FUNC_GPIO4>;

+			output-low;

 		};

-		pins_irq_ite {

-			pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;

+		pin_lt9611_1v8_en {

+			pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_GPIO19>;

+			output-low;

+		};

+

+		pin_lt9611_rst {

+			pinmux = <MT8365_PIN_20_LCM_RST__FUNC_GPIO20>;

+			output-low;

+		};

+

+		pin_lt9611_3v3_en {

+			pinmux = <MT8365_PIN_21_DSI_TE__FUNC_GPIO21>;

+			output-low;

+		};

+

+		pin_lt9611_intr {

+			pinmux = <MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125>;

 			input-enable;

+			bias-pull-up;

+		};

+

+		pin_dsi_sel {

+			pinmux = <MT8365_PIN_2_GPIO2__FUNC_GPIO2>;

+			output-low;

 		};

 	};

+#endif

 };

-- 

2.25.1

	file://0001-Add-dedicated-sb35-defconfig-and-dts-files.patch \

	file://0002-Remove-DPI-and-it66121-from-sb35-dts.patch \

	file://0001-Set-bootdelay-to-0-to-save-3secs-of-booting-time.patch \

	file://rs232.dts \

	file://spidev.dts \

/dts-v1/;

/plugin/;

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/mt8365-pinfunc.h>

/ {

	fragment@0 {

		target = <&pio>;

		__overlay__ {

			rs232_pins: rs232-pins {

				pins_rx {

					pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>;

					input-enable;

					bias-pull-up;

				};

				pins_tx_cts_rts {

					pinmux = <MT8365_PIN_38_UTXD1__FUNC_UTXD1>,

						<MT8365_PIN_39_URXD2__FUNC_UCTS1>,

						<MT8365_PIN_40_UTXD2__FUNC_URTS1>;

				};

				pins_rs232_shdn {

					pinmux = <MT8365_PIN_10_GPIO10__FUNC_GPIO10>;

					output-high;

				};

				pins_rs232_en {

					pinmux = <MT8365_PIN_8_GPIO8__FUNC_GPIO8>;

					output-high;

				};

			};

		};

	};

	fragment@1 {

		target = <&uart1>;

		__overlay__ {

			pinctrl-0 = <&rs232_pins>;

			pinctrl-names = "default";

			status = "okay";

		};

	};

};

/dts-v1/;

/plugin/;

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/mt8365-pinfunc.h>

/ {

	fragment@0 {

		target = <&pio>;

		__overlay__ {

			spi_pins: spi-pins {

				pins {

					pinmux = <MT8365_PIN_8_GPIO8__FUNC_SPI_CLK>,

						<MT8365_PIN_9_GPIO9__FUNC_SPI_CSB>,

						<MT8365_PIN_10_GPIO10__FUNC_SPI_MI>,

						<MT8365_PIN_11_GPIO11__FUNC_SPI_MO>;

					bias-disable;

				};

			};

		};

	};

	fragment@1 {

		target = <&spi>;

		__overlay__ {

			pinctrl-0 = <&spi_pins>;

			pinctrl-names = "default";

			mediatek,pad-select = <0>;

			status = "okay";

			spidev@0 {

				compatible = "mediatek,aiot-board";

				spi-max-frequency = <5000000>;

				reg = <0>;

			};

		};

	};

};

From f0a65dcb3dbd37388aa40250611fb07037eb3e97 Mon Sep 17 00:00:00 2001

From: Roy Chen <roy.chen@innocomm.com>

Date: Fri, 26 May 2023 15:33:28 +0800

Subject: [PATCH] Add stereo mode support

---

 arch/arm64/boot/dts/mediatek/mt8365-sb35.dts | 23 ++++---

 sound/soc/codecs/rt5509.c                    | 66 ++++++++++++++------

 sound/soc/codecs/rt5509.h                    |  7 +++

 sound/soc/mediatek/mt8365/mt8365-sb35.c      | 14 ++++-

 4 files changed, 80 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

index bae04d1ab18d..aa57f3444ea2 100644

--- a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

+++ b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

@@ -75,14 +75,19 @@ sound: sound {

 		pinctrl-5 = <&aud_pins_dmic>;

 		status = "okay";

-		dai-link {

-			sound-dai = <&afe>;

+		dai-link@0 {

 			dai-link-name = "2ND I2S BE";

-

-			codec-0 {

+			codec {

 				sound-dai = <&speaker_amp_left>;

 			};

 		};

+

+		dai-link@1 {

+			dai-link-name = "2ND I2S BE 2";

+			codec {

+				sound-dai = <&speaker_amp_right>;

+			};

+		};

 	};

 	reserved-memory {

@@ -321,17 +326,15 @@ speaker_amp_left:speaker_amp@34 {

 		reg = <0x34>;

 		status = "okay";

 		#sound-dai-cells = <0>;

-		rt5509,boost-mode = <1>;

-		rt5509,reg-settings = <0x1f 0x0352>;

+		rt5509,lrs = "left";

 	};

 	speaker_amp_right:speaker_amp@35 {

 		compatible = "richtek,rt5509";

 		reg = <0x35>;

-		status = "okay";		

-		#sound-dai-cells = <0>;		

-		rt5509,boost-mode = <1>;

-		rt5509,reg-settings = <0x1f 0x0352>;

+		status = "okay";

+		#sound-dai-cells = <0>;

+		rt5509,lrs = "right";

 	};

 	hdmi-bridge@3b {

diff --git a/sound/soc/codecs/rt5509.c b/sound/soc/codecs/rt5509.c

index a641797e407e..a43e9d67cd64 100644

--- a/sound/soc/codecs/rt5509.c

+++ b/sound/soc/codecs/rt5509.c

@@ -2705,8 +2705,6 @@ static const struct snd_kcontrol_new rt5509_component_snd_controls[] = {

 		rt5509_recv_model_put),

 	SOC_SINGLE_EXT("Calib_Start", SND_SOC_NOPM, 0, 0, 0,

 		rt5509_get_calib_flag, rt5509_put_calib_start),

-		

-	

 };

 static const struct snd_kcontrol_new rt5509_component_snd2_controls[] = {

@@ -2753,7 +2751,6 @@ static const struct snd_kcontrol_new rt5509_component_snd2_controls[] = {

 		rt5509_recv_model_put),

 	SOC_SINGLE_EXT("Ch2 Calib_Start", SND_SOC_NOPM, 0, 0, 0,

 		rt5509_get_calib_flag, rt5509_put_calib_start),

-		

 };

 static int rt5509_component_setting(struct snd_soc_component *component)

@@ -3259,9 +3256,24 @@ static inline int rt5509_parse_dt(struct device *dev,

 	struct device_node *param_np = NULL;

 	struct property *prop = NULL;

 	struct rt5509_proprietary_param *p_param = NULL;

+	const char *left_right_sel;

 	u32 len = 0;

 	int i = 0;

+	int ret = 0;

+	ret = device_property_read_string(dev, "rt5509,lrs", &left_right_sel);

+	if (ret >= 0) {

+		if (strcmp(left_right_sel, "left") == 0) {

+			pdata->left_right_sel = RT5509_LEFT_CHANNEL;

+		} else if (strcmp(left_right_sel, "right") == 0) {

+			pdata->left_right_sel = RT5509_RIGHT_CHANNEL;

+		} else {

+			pdata->left_right_sel = RT5509_LEFT_RIGHT_CHANNEL_MIXED;

+		}

+	} else {

+		pdata->left_right_sel = RT5509_LEFT_RIGHT_CHANNEL_MIXED;

+	}

+	

 	param_np = of_find_node_by_name(dev->of_node, "proprietary_param");

 	if (!param_np)

 		goto OUT_PARSE_DT;

@@ -3296,24 +3308,42 @@ static inline int rt5509_parse_dt(struct device *dev,

 }

 #endif /* #ifdef CONFIG_OF */

+static int rt5509_set_stereo_mode(const struct rt5509_chip *chip) {

+	int ret = 0;

+	u8 data = 0;

+

+	if (chip->pdata->left_right_sel == RT5509_LEFT_CHANNEL) {

+		data = 0x00;

+	} else if (chip->pdata->left_right_sel == RT5509_RIGHT_CHANNEL) {

+		data = 0x08;

+	} else {

+		// RT5509_LEFT_RIGHT_CHANNEL_MIXED

+		data = 0x04;

+	}

+

+	ret = rt5509_block_write(chip->i2c, RT5509_REG_I2SSEL, 1, &data);

+	if (ret < 0) {

+		dev_err(chip->dev, "channel selection failed ret=%d\n", ret);

+	} else {

+		dev_info(chip->dev, "channel selection = %d\n", chip->pdata->left_right_sel);

+	}

+

+	return ret;

+}

 static inline int rt5509_component_register(struct rt5509_chip *chip)

 {

-

-	if (chip->dev_cnt)

-	{

-			return devm_snd_soc_register_component(chip->dev,

-					       &rt5509_component_driver2,

-					       rt5509_ch2_i2s_dais,

-					       ARRAY_SIZE(rt5509_ch2_i2s_dais));

-	}else

-	{

-			return devm_snd_soc_register_component(chip->dev,

-					       &rt5509_component_driver,

-					       rt5509_i2s_dais,

-					       ARRAY_SIZE(rt5509_i2s_dais));

+	if (chip->dev_cnt) {

+		return devm_snd_soc_register_component(chip->dev,

+			&rt5509_component_driver2,

+			rt5509_ch2_i2s_dais,

+			ARRAY_SIZE(rt5509_ch2_i2s_dais));

+	} else {

+		return devm_snd_soc_register_component(chip->dev,

+			&rt5509_component_driver,

+			rt5509_i2s_dais,

+			ARRAY_SIZE(rt5509_i2s_dais));

 	}

-					       

 }

 static struct regmap_config rt5509_regmap_config = {

@@ -3413,7 +3443,7 @@ int rt5509_i2c_probe(struct i2c_client *client,

 	if(chip->dev_cnt==0)

 		rt5509_cal_init();

-	dev_info(chip->dev, "%s done\n", __func__);

+	rt5509_set_stereo_mode(chip);

 	return ret;

 probe_fail:

diff --git a/sound/soc/codecs/rt5509.h b/sound/soc/codecs/rt5509.h

index 203b8b2ceefc..1e0b63ae3599 100644

--- a/sound/soc/codecs/rt5509.h

+++ b/sound/soc/codecs/rt5509.h

@@ -36,6 +36,12 @@ enum {

 	RT5509_CHIP_REVD,

 };

+enum {

+	RT5509_LEFT_RIGHT_CHANNEL_MIXED,

+	RT5509_LEFT_CHANNEL,

+	RT5509_RIGHT_CHANNEL,

+};

+

 enum {

 	RT5509_CFG_GENERAL,

 	RT5509_CFG_BOOSTCONV,

@@ -56,6 +62,7 @@ struct rt5509_proprietary_param {

 struct rt5509_pdata {

 	struct rt5509_proprietary_param *p_param;

+	int left_right_sel;

 };

 struct rt5509_calib_classdev {

diff --git a/sound/soc/mediatek/mt8365/mt8365-sb35.c b/sound/soc/mediatek/mt8365/mt8365-sb35.c

index 27acef137e74..defdcf474fd5 100644

--- a/sound/soc/mediatek/mt8365/mt8365-sb35.c

+++ b/sound/soc/mediatek/mt8365/mt8365-sb35.c

@@ -67,6 +67,7 @@ enum {

 	DAI_LINK_VUL_CAPTURE,

 	/* BE */

 	DAI_LINK_2ND_I2S_INTF,

+	DAI_LINK_2ND_I2S_INTF2,

 	DAI_LINK_DMIC,

 	DAI_LINK_INT_ADDA,

 	DAI_LINK_NUM

@@ -75,13 +76,11 @@ enum {

 static const struct snd_soc_dapm_widget mt8365_sb35_widgets[] = {

 	SND_SOC_DAPM_MIC("PMIC MIC", NULL),

 	SND_SOC_DAPM_HP("Headphone", NULL),

-	SND_SOC_DAPM_OUTPUT("HDMI Out"),

 };

 static const struct snd_soc_dapm_route mt8365_sb35_routes[] = {

 	{"Headphone", NULL, "MT6357 Playback"},

 	{"MT6357 Capture", NULL, "PMIC MIC"},

-	{"HDMI Out", NULL, "2ND I2S Playback"},

 };

 static int mt8365_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,

@@ -294,6 +293,17 @@ static struct snd_soc_dai_link mt8365_sb35_dais[] = {

 		.dpcm_capture = 1,

 		SND_SOC_DAILINK_REG(i2s3),

 	},

+	[DAI_LINK_2ND_I2S_INTF2] = {

+		.name = "2ND I2S BE 2",

+		.no_pcm = 1,

+		.id = DAI_LINK_2ND_I2S_INTF2,

+		.dai_fmt = SND_SOC_DAIFMT_I2S |

+				SND_SOC_DAIFMT_NB_NF |

+				SND_SOC_DAIFMT_CBS_CFS,

+		.dpcm_playback = 1,

+		.dpcm_capture = 1,

+		SND_SOC_DAILINK_REG(i2s3),

+	},

 	[DAI_LINK_DMIC] = {

 		.name = "DMIC BE",

 		.no_pcm = 1,

-- 

2.39.2

From 3d835508c8f0ba77af87f35cf976adfcdd6a81d4 Mon Sep 17 00:00:00 2001

From: Roy Chen <roy.chen@innocomm.com>

Date: Tue, 23 May 2023 09:46:04 +0800

Subject: [PATCH] Audio RT5509 driver porting

---

 arch/arm64/boot/dts/mediatek/mt8365-sb35.dts |   25 +-

 sound/soc/codecs/Kconfig                     |    5 +

 sound/soc/codecs/Makefile                    |    3 +

 sound/soc/codecs/rt5509.c                    | 3483 ++++++++++++++++++

 sound/soc/codecs/rt5509.h                    |  481 +++

 sound/soc/mediatek/mt8365/mt8365-sb35.c      |   33 +-

 6 files changed, 4024 insertions(+), 6 deletions(-)

 create mode 100644 sound/soc/codecs/rt5509.c

 create mode 100644 sound/soc/codecs/rt5509.h

diff --git a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

index e8260faaab55..bae04d1ab18d 100644

--- a/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

+++ b/arch/arm64/boot/dts/mediatek/mt8365-sb35.dts

@@ -74,6 +74,15 @@ sound: sound {

 		pinctrl-4 = <&aud_pins_default>;

 		pinctrl-5 = <&aud_pins_dmic>;

 		status = "okay";

+

+		dai-link {

+			sound-dai = <&afe>;

+			dai-link-name = "2ND I2S BE";

+

+			codec-0 {

+				sound-dai = <&speaker_amp_left>;

+			};

+		};

 	};

 	reserved-memory {

@@ -307,14 +316,22 @@ &i2c1 {

 	clock-frequency = <100000>;

 	status = "okay";

-	rt5509_left: codec@34 {

-		compatible = "realtek,rt5514";

+	speaker_amp_left:speaker_amp@34 {

+		compatible = "richtek,rt5509";

 		reg = <0x34>;

+		status = "okay";

+		#sound-dai-cells = <0>;

+		rt5509,boost-mode = <1>;

+		rt5509,reg-settings = <0x1f 0x0352>;

 	};

-	rt5509_right: codec@35 {

-		compatible = "realtek,rt5514";

+	speaker_amp_right:speaker_amp@35 {

+		compatible = "richtek,rt5509";

 		reg = <0x35>;

+		status = "okay";		

+		#sound-dai-cells = <0>;		

+		rt5509,boost-mode = <1>;

+		rt5509,reg-settings = <0x1f 0x0352>;

 	};

 	hdmi-bridge@3b {

diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig

index a2fb0031b342..3977d89674d1 100644

--- a/sound/soc/codecs/Kconfig

+++ b/sound/soc/codecs/Kconfig

@@ -226,6 +226,7 @@ config SND_SOC_ALL_CODECS

 	imply SND_SOC_TLV320AIC3X_I2C

 	imply SND_SOC_TLV320AIC3X_SPI

 	imply SND_SOC_TPA6130A2

+	imply SND_SOC_RT5509

 	imply SND_SOC_TLV320DAC33

 	imply SND_SOC_TSCS42XX

 	imply SND_SOC_TSCS454

@@ -1963,4 +1964,8 @@ config SND_SOC_LPASS_TX_MACRO

 	select REGMAP_MMIO

 	tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)"

+config SND_SOC_RT5509

+	tristate "Richtek RT5509 Smart AMP"

+	depends on I2C

+

 endmenu

diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile

index 67423b98f96d..84bf12e93ca9 100644

--- a/sound/soc/codecs/Makefile

+++ b/sound/soc/codecs/Makefile

@@ -320,6 +320,8 @@ snd-soc-wm9713-objs := wm9713.o

 snd-soc-wm-hubs-objs := wm_hubs.o

 snd-soc-wsa881x-objs := wsa881x.o

 snd-soc-zl38060-objs := zl38060.o

+snd-soc-rt5509-objs := rt5509.o

+

 # Amp

 snd-soc-max9877-objs := max9877.o

 snd-soc-max98504-objs := max98504.o

@@ -664,6 +666,7 @@ obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO)	+= snd-soc-lpass-wsa-macro.o

 obj-$(CONFIG_SND_SOC_LPASS_VA_MACRO)	+= snd-soc-lpass-va-macro.o

 obj-$(CONFIG_SND_SOC_LPASS_RX_MACRO)	+= snd-soc-lpass-rx-macro.o

 obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO)	+= snd-soc-lpass-tx-macro.o

+obj-$(CONFIG_SND_SOC_RT5509)	+= snd-soc-rt5509.o

 # Mux

 obj-$(CONFIG_SND_SOC_SIMPLE_MUX)	+= snd-soc-simple-mux.o

diff --git a/sound/soc/codecs/rt5509.c b/sound/soc/codecs/rt5509.c

new file mode 100644

index 000000000000..a641797e407e

--- /dev/null

+++ b/sound/soc/codecs/rt5509.c

@@ -0,0 +1,3483 @@

+/*

+ * Copyright (C) 2019 MediaTek Inc.

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License version 2 as

+ * published by the Free Software Foundation.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

+ * See http://www.gnu.org/licenses/gpl-2.0.html for more details.

+ */

+

+#include <linux/module.h>

+#include <linux/kernel.h>

+#include <linux/version.h>

+#include <linux/err.h>

+#include <linux/i2c.h>

+#include <linux/delay.h>

+#include <sound/soc.h>

+#include <sound/tlv.h>

+#include <sound/pcm_params.h>

+#include <linux/debugfs.h>

+#include <linux/of.h>

+#include <linux/gpio.h>

+#include <linux/of_gpio.h>

+#include <linux/pm_runtime.h>

+

+#include "rt5509.h"

+

+#if IS_ENABLED(CONFIG_SND_SOC_MTK_AUDIO_DSP)

+#include "richtek_spm_cls.h"

+#endif

+

+/*---------------------------------------------------*/

+

+#include <linux/fs.h>

+#include <linux/uaccess.h>

+#include <linux/buffer_head.h>

+/* alsa sound header */

+#include <sound/soc.h>

+/* 64bit integer */

+#include <linux/math64.h>

+#include <sound/soc.h>

+

+#define RT5509_CALIB_MAGIC (5526789)

+

+static struct class *rt5509_cal_class;

+static int calib_status;

+

+enum {

+	RT5509_CALIB_CTRL_START = 0,

+	RT5509_CALIB_CTRL_DCROFFSET,

+	RT5509_CALIB_CTRL_N20DB,

+	RT5509_CALIB_CTRL_N15DB,

+	RT5509_CALIB_CTRL_N10DB,

+	RT5509_CALIB_CTRL_READOTP,

+	RT5509_CALIB_CTRL_READRAPP,

+	RT5509_CALIB_CTRL_WRITEOTP,

+	RT5509_CALIB_CTRL_WRITEFILE,

+	RT5509_CALIB_CTRL_END,

+	RT5509_CALIB_CTRL_ALLINONE,

+	RT5509_CALIB_CTRL_MAX,

+};

+ 

+static int rt5509_calib_get_dcroffset(struct rt5509_chip *chip)

+{

+

+	uint32_t delta_v = 0, vtemp = 0;

+	int ret = 0;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_VTEMP_TRIM);

+	if (ret < 0)

+		return ret;

+	vtemp = ret & 0xffff;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_VTHRMDATA);

+	if (ret < 0)

+		return ret;

+	ret &= 0xffff;

+	delta_v = (2730 - 400) * (ret - vtemp) / vtemp;

+	return delta_v;

+}

+

+static int rt5509_calib_chosen_db(struct rt5509_chip *chip, int choose)

+{

+	u32 data = 0;

+	uint8_t mode_store = 0;

+	int i = 0, ret = 0;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_BST_MODE);

+	if (ret < 0)

+		return ret;

+	mode_store = ret;

+

+	data = 0x0080;

+

+		ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_REQ, data);

+	if (ret < 0)

+		return ret;

+	switch (choose) {

+	case RT5509_CALIB_CTRL_N20DB:

+		data = 0x0ccc;

+		break;

+	case RT5509_CALIB_CTRL_N15DB:

+		data = 0x16c3;

+		break;

+	case RT5509_CALIB_CTRL_N10DB:

+		data = 0x287a;

+		break;

+	default:

+		return -EINVAL;

+	}

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_GAIN, data);	

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CALIB_CTRL);		

+	if (ret < 0)

+		return ret;

+	data = ret;

+	data |= 0x80;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_CTRL, data);		

+	if (ret < 0)

+		return ret;

+	mdelay(120);

+	while (i++ < 3) {

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CALIB_CTRL);	

+		if (ret < 0)

+			return ret;

+		if (ret & 0x01)

+			break;

+		mdelay(20);

+	}

+	data &= ~(0x80);

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_CTRL, data);

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_update_bits(chip->component, RT5509_REG_BST_MODE,		0x03, mode_store);

+	

+	if (ret < 0)

+		return ret;

+	

+	if (i > 3) {

+		dev_err(chip->dev, "over ready count\n");

+		return -EINVAL;

+	}

+	return snd_soc_component_read(chip->component, RT5509_REG_CALIB_OUT0);

+}

+

+static int rt5509_calib_read_otp(struct rt5509_chip *chip)

+{

+

+	int ret = 0;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_ISENSEGAIN);		

+	if (ret < 0)

+		return ret;

+	ret &= 0xffffff;

+	return ret;

+}

+

+static int rt5509_calib_write_otp(struct rt5509_chip *chip)

+{

+	uint8_t mode_store = 0;

+	uint32_t param = chip->calib_dev.rspk;

+	uint32_t param_store = 0;

+	uint32_t bst_th = 0;

+	int ret = 0;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_BST_TH1);	

+	if (ret < 0)

+		return ret;

+	bst_th = ret;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_BST_MODE);	

+	if (ret < 0)

+		return ret;

+	mode_store = ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_BST_TH1, 0x029b);

+	if (ret < 0)

+		return ret;

+	

+	ret = snd_soc_component_update_bits(chip->component, RT5509_REG_BST_MODE, 0x03, 0x02);

+	if (ret < 0)

+		return ret;

+		

+	ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_DCR, param);

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_OTPDIN);	

+	ret &= 0x00ffff;

+	ret |= 0xc50000;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_OTPDIN, ret);

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_OTPDIN, 0x81);

+	if (ret < 0)

+		return ret;

+	msleep(100);

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_OTPCONF, 0x00);

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_update_bits(chip->component, RT5509_REG_BST_MODE,0x03, mode_store);

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_BST_TH1, bst_th);	

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_CALIB_DCR, 0x00);	

+	if (ret < 0)

+		return ret;

+

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_OTPCONF, 0x82);	

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_write(chip->component, RT5509_REG_OTPCONF, 0x00);	

+	if (ret < 0)

+		return ret;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CALIB_DCR);		

+	param_store = ret & 0xffffff;

+	dev_info(chip->dev, "store %08x, put %08x\n", param_store,

+		 param);

+	if (param_store != param)

+		return -EINVAL;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_OTPDIN);	

+	dev_info(chip->dev, "otp_din = 0x%08x\n", ret);

+	if ((ret & 0xff0000) != 0xc50000)

+		return -EINVAL;

+	chip->calibrated = 1;

+	return 0;

+}

+

+static int rt5509_calib_rwotp(struct rt5509_chip *chip, int choose)

+{

+	int ret = 0;

+

+	dev_info(chip->dev, "%s\n", __func__);

+	switch (choose) {

+	case RT5509_CALIB_CTRL_READOTP:

+		ret = rt5509_calib_read_otp(chip);

+		break;

+	case RT5509_CALIB_CTRL_WRITEOTP:

+		ret = rt5509_calib_write_otp(chip);

+		break;

+	default:

+		return -EINVAL;

+	}

+	return ret;

+}

+

+static int rt5509_calib_read_rapp(struct rt5509_chip *chip)

+{

+	int ret = 0;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_RAPP);		

+	if (ret < 0)

+		return ret;

+	ret &= 0xffffff;

+	return ret;

+}

+

+static int rt5509_calib_write_file(struct rt5509_chip *chip)

+{

+	return 0;

+}

+

+static int rt5509_calib_start_process(struct rt5509_chip *chip)

+{

+	int ret = 0;

+

+	dev_info(chip->dev, "%s\n", __func__);

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CHIPEN);	

+	if (ret < 0)

+		return ret;

+	if (!(ret & RT5509_SPKAMP_ENMASK)) {

+		dev_err(chip->dev, "class D not turn on\n");

+		return -EINVAL;

+	}

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_I2CBCKLRCKCONF);		

+	if (ret < 0)

+		return ret;

+	if (ret & 0x08) {

+		dev_err(chip->dev, "BCK loss\n");

+		return -EINVAL;

+	}

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CALIB_REQ);		

+	if (ret < 0)

+		return ret;

+	chip->pilot_freq = ret & 0xffff;

+	return 0;

+}

+

+static int rt5509_calib_end_process(struct rt5509_chip *chip)

+{

+	dev_info(chip->dev, "%s\n", __func__);

+	return  snd_soc_component_write(chip->component, RT5509_REG_CALIB_REQ,chip->pilot_freq);

+}

+

+static int rt5509_calib_trigger_read(struct rt5509_calib_classdev *cdev)

+{

+	struct rt5509_chip *chip = container_of(cdev,

+						struct rt5509_chip, calib_dev);

+	int ret = 0;

+

+	dev_dbg(chip->dev, "%s\n", __func__);

+	ret = rt5509_calib_start_process(chip);

+	if (ret < 0) {

+		dev_err(chip->dev, "start fail\n");

+		dev_err(chip->dev, "bck not valid or amp not turn on\n");

+		goto out_trigger_read;

+	}

+	ret = rt5509_calib_get_dcroffset(chip);

+	if (ret < 0) {

+		cdev->dcr_offset = 0xffffffff;

+		goto out_trigger_read;

+	}

+	cdev->dcr_offset = ret;

+	dev_dbg(chip->dev, "dcr_offset -> %d\n", cdev->dcr_offset);

+	ret = rt5509_calib_chosen_db(chip, RT5509_CALIB_CTRL_N15DB);

+	if (ret < 0) {

+		cdev->n15db = 0xffffffff;

+		goto out_trigger_read;

+	}

+	cdev->n15db = ret;

+	dev_dbg(chip->dev, "n15db -> 0x%08x\n", cdev->n15db);

+	ret = rt5509_calib_rwotp(chip, RT5509_CALIB_CTRL_READOTP);

+	if (ret < 0) {

+		cdev->gsense_otp = 0xffffffff;

+		goto out_trigger_read;

+	}

+	cdev->gsense_otp = ret;

+	dev_dbg(chip->dev, "gsense_otp -> 0x%08x\n", cdev->gsense_otp);

+	ret = rt5509_calib_read_rapp(chip);

+	if (ret < 0) {

+		cdev->rapp = 0xffffffff;

+		goto out_trigger_read;

+	}

+	cdev->rapp = ret;

+	dev_dbg(chip->dev, "rapp -> 0x%08x\n", cdev->rapp);

+	return 0;

+out_trigger_read:

+	return ret;

+}

+

+static int rt5509_calib_trigger_write(struct rt5509_calib_classdev *cdev)

+{

+	struct rt5509_chip *chip = container_of(cdev,

+						struct rt5509_chip, calib_dev);

+	int ret = 0;

+

+	dev_dbg(chip->dev, "%s\n", __func__);

+	ret = rt5509_calib_rwotp(chip, RT5509_CALIB_CTRL_WRITEOTP);

+	if (ret < 0)

+		goto out_trigger_write;

+	ret = rt5509_calib_write_file(chip);

+	if (ret < 0)

+		goto out_trigger_write;

+	ret = rt5509_calib_end_process(chip);

+	if (ret < 0)

+		goto out_trigger_write;

+	return 0;

+out_trigger_write:

+	return ret;

+}

+

+static int64_t rt5509_integer_dcr_calculation(int index, uint32_t n_db)

+{

+	int64_t a = 0, x = 0;

+	int64_t coeffi = 0;

+	int i = 0;

+	int64_t ret = 0;

+

+	switch (index) {

+	case RT5509_CALIB_CTRL_N20DB:

+		coeffi = 81051042;

+		break;

+	case RT5509_CALIB_CTRL_N15DB:

+		coeffi = 25630590;

+		break;

+	case RT5509_CALIB_CTRL_N10DB:

+		coeffi = 8105104;

+		break;

+	default:

+		return -1;

+	}

+	a = n_db * coeffi;

+	x = 1 << 24;

+	for (i = 0; i < 10; i++)

+		x = div_s64(((x * x + a) >> 1), x);

+	ret = 1;

+	ret <<= 32;

+	ret *= 10000000;

+	return div_s64(ret, x);

+}

+

+#define RefT (-40)

+#define alpha_r (265)

+static int rt5509_calib_trigger_calculation(struct rt5509_calib_classdev *cdev)

+{

+	struct rt5509_chip *chip = container_of(cdev,

+						struct rt5509_chip, calib_dev);

+	int64_t dcr_n15i = 0, dcr_i = 0;

+	int64_t alpha_rappi = 0, rappi = 0;

+	int64_t rspki = 0;

+	int64_t rspk_mini = 0, rspk_maxi = 0;

+

+	dev_info(chip->dev, "dcr_offset = 0x%08x\n", cdev->dcr_offset);

+	dev_info(chip->dev, "n15db reg = 0x%08x\n", cdev->n15db);

+	dev_info(chip->dev, "gsense_otp reg = 0x%08x\n", cdev->gsense_otp);

+	dcr_n15i = rt5509_integer_dcr_calculation(RT5509_CALIB_CTRL_N15DB,

+						  cdev->n15db);

+	if (dcr_n15i < 0)

+		return -EINVAL;

+	dcr_i = dcr_n15i;

+	alpha_rappi = cdev->alphaspk;

+	rappi = cdev->rapp;

+	rappi <<= 9;

+	dev_info(chip->dev, "rappi = %llx\n", rappi);

+	rspki = div_s64((dcr_i * cdev->gsense_otp), 8);

+	rspki *= (cdev->alphaspk + 25);

+	rspki = div_s64(rspki, (alpha_r + RefT));

+	rspki = div_s64(rspki, 1048576);

+	dev_info(chip->dev, "pre rspki = %llx\n", rspki);

+	rspki -= (div_s64((rappi * (alpha_rappi + 25)), (alpha_rappi + 50)));

+	dev_info(chip->dev, "post rspki = %llx\n", rspki);

+	rspk_mini = cdev->rspkmin;

+	rspk_mini <<= 32;

+	rspk_maxi = cdev->rspkmax;

+	rspk_maxi <<= 32;

+	if ((rspki * 80) < rspk_mini || (rspki * 80) > rspk_maxi) {

+		dev_err(chip->dev, "rspki over range\n");

+		return -EINVAL;

+	}

+	rspki >>= 9;

+	cdev->rspk = (uint32_t)rspki;

+	cdev->rspk &= 0xffffff;

+	dev_info(chip->dev, "rspk = 0x%08x\n", cdev->rspk);

+	return 0;

+}

+

+void rt5509_calib_destroy(struct rt5509_chip *chip)

+{

+	dev_dbg(chip->dev, "%s\n", __func__);

+	device_unregister(chip->calib_dev.dev);

+}

+EXPORT_SYMBOL_GPL(rt5509_calib_destroy);

+

+int rt5509_calib_create(struct rt5509_chip *chip)

+{

+	struct rt5509_calib_classdev *pcalib_dev = &chip->calib_dev;

+	int ret = 0;

+

+	dev_dbg(chip->dev, "%s\n", __func__);

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_OTPDIN);	

+	ret &= 0xff0000;

+

+	if (ret == 0xc50000)

+		chip->calibrated = 1;

+

+	ret = snd_soc_component_read(chip->component, RT5509_REG_CALIB_DCR);	

+	ret &= 0xffffff;

+	pcalib_dev->rspk = ret;

+	/* default rspk min,max,alphspk */

+	pcalib_dev->rspkmin = 10;

+	pcalib_dev->rspkmax = 160;

+	pcalib_dev->alphaspk = 265;

+	pcalib_dev->trigger_read = rt5509_calib_trigger_read;